u-boot.git/drivers/net/phy, branch v2026.04

net: phy: mscc: Enable RMII clock output for VSC8541 PHY

2026-02-11T08:41:26+00:00

Set RMII reference clock output to enabled (1) by default for VSC8541
PHY in RMII mode. The RMII specification requires a 50MHz reference
clock, and many board designs expect the PHY to provide this clock to
the MAC controller.

Previously, the driver defaulted rmii_clk_out to 0 (disabled) for all
interface modes, which caused the PHY to not output the required 50MHz
clock. This resulted in MAC-PHY communication failures and prevented
network operations like DHCP from working on RMII-configured boards.

This change alligns with the hardware power-up default behavior and
aligns with both the generic PHY driver and Linux MSCC PHY driver
implementations.

Signed-off-by: Pranav Tilak 
Signed-off-by: Michal Simek 
Link: https://lore.kernel.org/r/20260129081054.1703479-1-pranav.vinaytilak@amd.com

net: phy: mscc: allow RGMII with internal delay for the VSC8541

2026-02-06T15:42:45+00:00

Add the missing RGMII modes with internal delay for the VSC8541.

Fixes: a5fd13ad1913 ("net: phy: MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541")
Signed-off-by: Charles Perry

net: phy: aquantia: add support for Marvell CUX3410 10Gb PHY

2026-02-04T08:04:36+00:00

The CUX3410 is similar to AQR113C. The main difference is CUX3410 does not
support MACSEC.

Signed-off-by: Bo-Cun Chen

net: phy: micrel_ksz90x1: support forced GIGE master for KSZ9031

2026-01-15T10:09:28+00:00

The micrel KSZ9031 phy has a optional clock pin (CLK125_NDO) which can be
used as reference clock for the MAC unit. The clock signal must meet the
RGMII requirements to ensure the correct data transmission between the
MAC and the PHY. The KSZ9031 phy does not fulfill the duty cycle
requirement if the phy is configured as slave. For a complete
describtion look at the errata sheets: DS80000691D or DS80000692D.

The errata sheet recommends to force the phy into master mode whenever
there is a 1000Base-T link-up as work around. Only set the
"micrel,force-master" property if you use the phy reference clock provided
by CLK125_NDO pin as MAC reference clock in your application.

Attention: this workaround is only usable if the link partner can
be configured to slave mode for 1000Base-T.

This follows linux implementation in commit
e1b505a60366 ("net: phy: micrel: add 125MHz reference clock workaround")

Signed-off-by: Markus Niebel 
Signed-off-by: Max Merchel

net: phy: micrel_ksz90x1: disable asymmetric pause for KSZ9031 and KSZ9021

2026-01-15T10:09:28+00:00

Disable the support due to chip errata and call genphy_config_aneg
instead of genphy_config. For a complete describtion look at the
KSZ9031 errata sheets: DS80000691D or DS80000692D.

Micrel KSZ9021 has no errata, but has the same issue with Asymmetric Pause.
This patch apply the same workaround as the one for KSZ9031.

This follows linux implementation in commits
3aed3e2a143c ("net: phy: micrel: add Asym Pause workaround")
407d8098cb1a ("net: phy: micrel: add Asym Pause workaround for KSZ9021")

Signed-off-by: Markus Niebel 
Signed-off-by: Max Merchel

net: phy: marvell10g: Fix PHY mode bitmap handling

2026-01-15T10:09:28+00:00

Replace PHY interface mode bitmap handling with comparison test to match
U-Boot PHY subsystem behavior. U-Boot currently implements only single PHY
interface mode for each PHY. Linux currently uses bitmap of PHY interface
modes for each PHY.

The reason why in Linux uses bitmap of supported interface modes is so
that Linux can select the best serdes mode switching behavior for the PHY.

For example if the host only supports 10gbase-r serdes mode, then the PHY
must always talk to the host in 10gbase-r mode, even if the RJ-45 copper
speed was autonegotiated to lower speed (i.e. 1Gbps).

If the host supports both 10gbase-r and sgmii serdes modes, we want the
PHY to switch to sgmii if the RJ-45 speed is 1000/100/10, and to switch
to 10gbase-r if the RJ-45 speed is 10000.

U-Boot does not implement this functionality yet, therefore remove modes
which cannot be currently supported and switch mv_test_bit() to plain
mode comparison.

Fixes: b6fcab0728cb ("net: phy: marvell10g: Adapt Marvell 10G PHY driver from Linux")
Signed-off-by: Marek Vasut

dm: core: Default to using DEVRES outside of xPL

2026-01-09T15:08:14+00:00

The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).

This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.

Reviewed-by: Michael Trimarchi 
Signed-off-by: Tom Rini

Merge tag 'v2026.01-rc4' into next

2025-12-08T19:17:27+00:00

Prepare v2026.01-rc4

net: phy: aquantia: use generic firmware loader

2025-12-01T09:37:06+00:00

Aquantia PHYs are being used w/o SPI flash in some routers recently.
Current firmware loader only attempts to load from FS on top of MMC,
limiting the use on many devices.

Removed the old firmware loader, migrate to generic script based firmware
loader to allow a wider range and runtime override of firmware source.
(e.g., MMC, USB, UBIFS).

Tested on Buffalo WXR18000BE10P with UBIFS.

Signed-off-by: Beiyan Yun

net: phy: aquantia: refactor firmware upload helpers

2025-12-01T09:37:06+00:00

Split `aquantia_upload_firmware` into `aquantia_upload_firmware`
and `aquantia_do_upload_firmware` to prepare for fwloader change.

Signed-off-by: Beiyan Yun