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<title>u-boot.git/drivers/net/tsec.c, branch v2009.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>net: tsec: Fix Marvell 88E1121R phy init</title>
<updated>2008-12-05T06:51:54+00:00</updated>
<author>
<name>Anatolij Gustschin</name>
<email>agust@denx.de</email>
</author>
<published>2008-12-02T09:31:04+00:00</published>
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<content type='text'>
This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:

Marvell 88E1121R phy can be hardware-configured
to share MDC/MDIO and interrupt pins for both ports
P0 and P1 (e.g. as configured on socrates board).
Port 0 interrupt pin will be shared by both ports
in such configuration. After booting Linux and
configuring eth0 interface, port 0 phy interrupts
are enabled. After rebooting without proper eth0
interface shutdown port 0 phy interrupts remain
enabled so any change on port 0 (link status, etc.)
cause assertion of the interrupt. Now booting Linux
and configuring eth1 interface will cause permanent
phy interrupt storm as the registered phy 1 interrupt
handler doesn't acknowledge phy 0 interrupts. This
of course should be fixed in Linux driver too.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:

Marvell 88E1121R phy can be hardware-configured
to share MDC/MDIO and interrupt pins for both ports
P0 and P1 (e.g. as configured on socrates board).
Port 0 interrupt pin will be shared by both ports
in such configuration. After booting Linux and
configuring eth0 interface, port 0 phy interrupts
are enabled. After rebooting without proper eth0
interface shutdown port 0 phy interrupts remain
enabled so any change on port 0 (link status, etc.)
cause assertion of the interrupt. Now booting Linux
and configuring eth1 interface will cause permanent
phy interrupt storm as the registered phy 1 interrupt
handler doesn't acknowledge phy 0 interrupts. This
of course should be fixed in Linux driver too.

Signed-off-by: Anatolij Gustschin &lt;agust@denx.de&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>rename CFG_ macros to CONFIG_SYS</title>
<updated>2008-10-18T19:54:03+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2008-10-16T13:01:15+00:00</published>
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<content type='text'>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
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<pre>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>enable 10/100M at VSC8601 at tsec driver</title>
<updated>2008-10-14T05:29:37+00:00</updated>
<author>
<name>Andre Schwarz</name>
<email>andre.schwarz@matrix-vision.de</email>
</author>
<published>2008-08-19T14:07:03+00:00</published>
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<content type='text'>
Currently VSC8601 doesn't link with 10/100M partners if the
EEPROM/Strapping is not set up.
Setting the auto-neg register fixes this.

Signed-off-by: Andre Schwarz &lt;andre.schwarz@matrix-vision.de&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
Currently VSC8601 doesn't link with 10/100M partners if the
EEPROM/Strapping is not set up.
Setting the auto-neg register fixes this.

Signed-off-by: Andre Schwarz &lt;andre.schwarz@matrix-vision.de&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Support for multiple SGMII/TBI interfaces for TSEC ethernet</title>
<updated>2008-09-16T16:32:45+00:00</updated>
<author>
<name>Peter Tyser</name>
<email>ptyser@xes-inc.com</email>
</author>
<published>2008-09-16T15:04:47+00:00</published>
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<content type='text'>
Fix TBI PHY accesses to use the proper offset in CPU register space. The
previous code would incorrectly access the TBI PHY by reading/writing to CPU
register space at the same location as would be used to access external PHYs.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
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<pre>
Fix TBI PHY accesses to use the proper offset in CPU register space. The
previous code would incorrectly access the TBI PHY by reading/writing to CPU
register space at the same location as would be used to access external PHYs.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Add SGMII support to the tsec</title>
<updated>2008-09-03T04:18:15+00:00</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2008-08-31T21:33:27+00:00</published>
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<id>2abe361c03b43e6dcf68f54e96b5c05156c49284</id>
<content type='text'>
Adds support for configuring the TBI to talk properly with the SerDes.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
Adds support for configuring the TBI to talk properly with the SerDes.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Pass in tsec_info struct through tsec_initialize</title>
<updated>2008-09-03T04:18:15+00:00</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2008-08-31T21:33:26+00:00</published>
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<id>75b9d4ae0d69f214eab641caf12ce8af83a39a42</id>
<content type='text'>
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>tsec: Move tsec.h to include/</title>
<updated>2008-09-03T04:18:15+00:00</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2008-08-31T21:33:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dd3d1f56a01f460d560766126ee7dfed2ea9bc10'/>
<id>dd3d1f56a01f460d560766126ee7dfed2ea9bc10</id>
<content type='text'>
This is to prepare the way for board code passing in the tsec_info structure

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
This is to prepare the way for board code passing in the tsec_info structure

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>PHY: Add support for the M88E1121R Marvell chip.</title>
<updated>2008-09-03T04:18:14+00:00</updated>
<author>
<name>Sergei Poselenov</name>
<email>sposelenov@emcraft.com</email>
</author>
<published>2008-06-06T13:52:44+00:00</published>
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<id>d23dc394aa69093b6326ad917db04dc0d1aff3f8</id>
<content type='text'>
Signed-off-by: Yuri Tikhonov &lt;yur@emcraft.com&gt;
Signed-off-by: Sergei Poselenov &lt;sposelenov@emcraft.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
Signed-off-by: Yuri Tikhonov &lt;yur@emcraft.com&gt;
Signed-off-by: Sergei Poselenov &lt;sposelenov@emcraft.com&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: Conditional COBJS inclusion of network drivers</title>
<updated>2008-06-10T06:21:05+00:00</updated>
<author>
<name>Shinya Kuribayashi</name>
<email>skuribay@ruby.dti.ne.jp</email>
</author>
<published>2008-06-09T14:37:44+00:00</published>
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<id>3b904ccb93c3196727e2e9870cb1df903cab19ad</id>
<content type='text'>
Replace COBJS-y with appropriate driver config names.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
Replace COBJS-y with appropriate driver config names.

Signed-off-by: Shinya Kuribayashi &lt;skuribay@ruby.dti.ne.jp&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Add Marvell 88E1118 support for TSEC</title>
<updated>2008-05-24T03:25:19+00:00</updated>
<author>
<name>Ron Madrid</name>
<email>ron_madrid@sbcglobal.net</email>
</author>
<published>2008-05-23T22:37:05+00:00</published>
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<content type='text'>
Signed-off-by: Ron Madrid &lt;ron_madrid@sbcglobal.net&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
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<pre>
Signed-off-by: Ron Madrid &lt;ron_madrid@sbcglobal.net&gt;
Signed-off-by: Ben Warren &lt;biggerbadderben@gmail.com&gt;
</pre>
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</content>
</entry>
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