u-boot.git/drivers/net/tsec.c, branch v2009.08 Unnamed repository; edit this file 'description' to name the repository. tsec: Wait for auto-negotiation to complete without link 2009-08-21T17:35:30+00:00 Peter Tyser ptyser@xes-inc.com 2009-02-04T21:14:05+00:00 b1e849f2201bbbf3ca81fde164f154f9caf7f0e9 Previously, waiting for auto-negotiation would only occur if a valid link had been detected. Problems arose when attempting to use a tsec immediately after bootup but before link was achieved, eg: => dhcp Auto-neg error, defaulting to 10BT/HD eTSEC1: No link. Auto-neg error, defaulting to 10BT/HD eTSEC2: No link. => With this patch applied the same operation as above resulted in: => dhcp Waiting for PHY auto negotiation to complete. done Enet starting in 1000BT/FD Speed: 1000, full duplex Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com> 
Previously, waiting for auto-negotiation would only occur if a valid
link had been detected.  Problems arose when attempting to use a
tsec immediately after bootup but before link was achieved, eg:
=> dhcp
Auto-neg error, defaulting to 10BT/HD
eTSEC1: No link.
Auto-neg error, defaulting to 10BT/HD
eTSEC2: No link.
=>

With this patch applied the same operation as above resulted in:
=> dhcp
Waiting for PHY auto negotiation to complete. done
Enet starting in 1000BT/FD
Speed: 1000, full duplex

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Update Freescale copyrights to remove "All Rights Reserved" 2009-07-29T07:59:22+00:00 Kumar Gala kumar.gala@freescale.com 2009-07-29T02:49:52+00:00 4c2e3da82dc2b7f8b39b7f1d57f570e4bc5caa6d "All Rights Reserved" conflicts with the GPL. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> 
"All Rights Reserved" conflicts with the GPL.

Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
P2020RDB Added support of Vitesse PHYs VSC8641(RGMII) and VSC8221(SGMII) 2009-07-23T05:53:44+00:00 Poonam Aggrwal poonam.aggrwal@freescale.com 2009-07-02T10:45:13+00:00 b7fe25d2a8d1cede401d09e1f9c84f8fe47bdbb1 These PHYs are on P2020RDB platform. Also revamped Freescale copyright message in drivers/net/tsec.c. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com> 
These PHYs are on P2020RDB platform.

Also revamped Freescale copyright message in drivers/net/tsec.c.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
net: tsec - fix dereferencing type-punned pointer will break strict-aliasing rules warning 2009-07-23T05:53:44+00:00 Kim Phillips kim.phillips@freescale.com 2009-07-17T17:17:00+00:00 88ad3fd91c83a4343b25385fd78fd8e29ebb723f fix this gcc 4.4 warning: tsec.c: In function 'tsec_init': tsec.c:200: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com> 
fix this gcc 4.4 warning:

tsec.c: In function 'tsec_init':
tsec.c:200: warning: dereferencing type-punned pointer will break strict-aliasing rules

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
tsec: Add support for BCM5482S PHY 2009-06-15T07:13:54+00:00 Zach LeRoy zleroy@xes-inc.com 2009-05-22T15:26:33+00:00 091dc9f6adaf572b067ae91af92c4e7db33d7903 Signed-off-by: Zach LeRoy <zleroy@xes-inc.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com> 
Signed-off-by: Zach LeRoy <zleroy@xes-inc.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
tsec: report when there is no vendor specific PHY support 2009-03-09T23:08:04+00:00 Paul Gortmaker paul.gortmaker@windriver.com 2009-03-09T23:07:53+00:00 0452352df118bc9dd684a056aaaa5fb4aed1178a Commit af1c2b84 added a generic phy support, with an ID of zero and a 32 bit mask; meaning that it will match on any PHY ID. The problem is that there is a test that checked if a matching PHY was found, and if not, it printed the non-matching ID. But since there will always be a match (on the generic PHY, worst case), this test will never trip. In the case of a misconfigured PHY address, or of a PHY that isn't explicitly supported outside of the generic support, you will never see the ID of 0xffffffff, or the ID of the real (but unsupported) chip. It will silently fall through onto the generic support. This change makes that test useful again, and ensures that the selection of generic PHY support doesn't happen without some sort of notice. It also makes it explicitly clear that the generic PHY must be last in the PHY table. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Andy Fleming <afleming@freescale.com> 
Commit af1c2b84 added a generic phy support, with an ID of zero
and a 32 bit mask; meaning that it will match on any PHY ID.

The problem is that there is a test that checked if a matching
PHY was found, and if not, it printed the non-matching ID.
But since there will always be a match (on the generic PHY,
worst case), this test will never trip.

In the case of a misconfigured PHY address, or of a PHY that
isn't explicitly supported outside of the generic support,
you will never see the ID of 0xffffffff, or the ID of the
real (but unsupported) chip.  It will silently fall through
onto the generic support.

This change makes that test useful again, and ensures that
the selection of generic PHY support doesn't happen without
some sort of notice.  It also makes it explicitly clear that
the generic PHY must be last in the PHY table.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Added Vitesse VSC8211 definitions to TSEC driver 2009-02-23T07:49:33+00:00 Pieter Henning phenning@vastech.co.za 2009-02-23T07:17:15+00:00 736323a490b664ec0edc3ddb2c1c4a6824db45c6 Added the struct containing PHY settings for the Vitesse VSC8211 phy to the phy_info list in tsec.c Signed-off-by: Pieter Henning <phenning@vastech.co.za> Signed-off-by: Ben Warren <biggerbadderben@gmail.com> 
Added the struct containing PHY settings for the Vitesse VSC8211 phy to
the phy_info list in tsec.c

Signed-off-by: Pieter Henning <phenning@vastech.co.za>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
tsec: Fix a bug in soft-resetting 2009-02-10T06:52:32+00:00 Andy Fleming afleming@freescale.com 2009-02-04T00:26:41+00:00 9e5be8214ba751436e57c3be044bf6dccb9a6687 SOFT_RESET must be asserted for at least 3 TX clocks. Usually, that's about 30 clock cycles, so it's been mostly working. But we had no guarantee, and at slower bitrates, it's just over a microsecond (over 1000 clock cycles). This enforces a 2 microsecond gap between assertion and deassertion. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com> 
SOFT_RESET must be asserted for at least 3 TX clocks.  Usually, that's about 30
clock cycles, so it's been mostly working.  But we had no guarantee, and at
slower bitrates, it's just over a microsecond (over 1000 clock cycles).  This
enforces a 2 microsecond gap between assertion and deassertion.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Marvell 88E1118 interrupt fix 2009-01-29T07:59:28+00:00 Ron Madrid ron_madrid@sbcglobal.net 2009-01-29T00:17:21+00:00 12a8b9db12f82a189ff143a58731007f5469da61 This patch adjusts the LED control so that interrupt lines are not reading LEDs and effectively causing indefinite interrupts to the controller. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com> 
This patch adjusts the LED control so that interrupt lines are not reading LEDs
and effectively causing indefinite interrupts to the controller.

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
net: tsec: Fix Marvell 88E1121R phy init 2008-12-05T06:51:54+00:00 Anatolij Gustschin agust@denx.de 2008-12-02T09:31:04+00:00 23afaba65ec5206757e589ef334a8b38168c045f This patch tries to ensure that phy interrupt pin won't be asserted after booting. We experienced following issues with current 88E1121R phy init: Marvell 88E1121R phy can be hardware-configured to share MDC/MDIO and interrupt pins for both ports P0 and P1 (e.g. as configured on socrates board). Port 0 interrupt pin will be shared by both ports in such configuration. After booting Linux and configuring eth0 interface, port 0 phy interrupts are enabled. After rebooting without proper eth0 interface shutdown port 0 phy interrupts remain enabled so any change on port 0 (link status, etc.) cause assertion of the interrupt. Now booting Linux and configuring eth1 interface will cause permanent phy interrupt storm as the registered phy 1 interrupt handler doesn't acknowledge phy 0 interrupts. This of course should be fixed in Linux driver too. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com> 
This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:

Marvell 88E1121R phy can be hardware-configured
to share MDC/MDIO and interrupt pins for both ports
P0 and P1 (e.g. as configured on socrates board).
Port 0 interrupt pin will be shared by both ports
in such configuration. After booting Linux and
configuring eth0 interface, port 0 phy interrupts
are enabled. After rebooting without proper eth0
interface shutdown port 0 phy interrupts remain
enabled so any change on port 0 (link status, etc.)
cause assertion of the interrupt. Now booting Linux
and configuring eth1 interface will cause permanent
phy interrupt storm as the registered phy 1 interrupt
handler doesn't acknowledge phy 0 interrupts. This
of course should be fixed in Linux driver too.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>