Extend ENETC driver to support i.MX952 platform where 2 ENETC
controllers are located on different PCIe buses.

Key changes:
- Add enetc_dev_id_imx() to derive device ID from device tree "reg"
  property for i.MX952, mapping bus_devfn values 0x0 and 0x100 to device
  IDs 0 and 1 respectively
- Implement imx952_netcmix_init() to configure MII protocol and PCS
  settings based on PHY mode parsed from device tree
- Add i.MX952 to FSL_ENETC_NETC_BLK_CTRL Kconfig dependencies

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

The iMX and LS platforms use different bits in the same register to
set duplex, but their logics are opposite.
The current settings will result in unexpected configurations in
RGMII mode.

Fixes: e6df2f5e22c6 ("net: fsl_enetc: Update enetc driver to support i.MX95")
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>

devm_kzalloc needs to pass udevice for first parameter, this phy driver
wrongly pass the priv in phy_device. And because the dev in phy_device
is only valid after phy_connect, in probe phase this dev is NULL, so
we can't use devm_kzalloc, replace it with kzalloc.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

This is similar to the VSC8574 according to the Linux commit that adds
support for it [1].

This was tested on an HX1000 board with SGMII (PIC64-HX SoC which has a
GEM MAC).

[1]: https://lore.kernel.org/all/dfabe39a52efcd2cfff9358f271b8673143503b8.1480497966.git.neill.whillans@codethink.co.uk/

Signed-off-by: Charles Perry <charles.perry@microchip.com>
Reviewed-by: Manikandan Muralidharan <manikandan.m@microchip.com>

A fixed gigabit link on a non-gigabit controller is only rejected
during PHY init (even though there is no PHY to init), because, on
device-tree parsing, the controller is not probed, and it is still
unknown whether it is gigabit-capable.

This code was only tested on emulator with a full-duplex RGMII
interface, but is expected to work in GMII or half-duplex as well.

Signed-off-by: Christian DREHER <christian.dreher@nanoxplore.com>

Cadence Ethernet MAC has a feature named user_io, which provides
some input and some output signals for arbitrary purpose in the SoC.
From the driver code, I understand that, on Atmel SoC, it is used to
drive the PHY mode.

At least on Cadence IP7014 r1p12, this feature is optional, and I am
working on a SoC that does not instantiate it. The presence of this
feature is advertised in DCFG1, this patch merely disables the access
to the user_io register based on this information.

I did not apply this change to the non-gigabit capable versions of
the IP, as I do not have documentation for them, and a new non-gigabit
instance is unlikely to appear. I prefer avoiding regressions on old
systems.

Signed-off-by: Christian DREHER <christian.dreher@nanoxplore.com>

The MACB uses specific address registers (SA Top and Bottom) to
filter source or destination MAC addresses.
On the Gigabit Ethernet version, SA1B is @0x88.
On the non-GEM version, SA1B is @0x98.

Before this commit, the code was always writing 0x98. By chance,
on GEM, this is the address of SA3B, allowing the driver to work
anyway.

The motivation for this change is to be able to use the driver on
an instance of the GEM with less than 4 SA registers.

Signed-off-by: Christian DREHER <christian.dreher@nanoxplore.com>

It does not exist in my setup (an on-going arm64 SoC), and removing
it does not cause any missing declaration, but some code called when
CONFIG_CLK is missing calls get_macb_pclk_rate, which is only defined
in arch/arm/mach-at91/include/mach/clk.h

Signed-off-by: Christian DREHER <christian.dreher@nanoxplore.com>

The ADIN1200 chip is register compatible with the ADIN1300, but only
supports 10/100 Mbit.

Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>

Replace the proprietary airoha,pnswap-rx / airoha,pnswap-tx boolean
device tree properties with the standard rx-polarity and tx-polarity
properties defined in phy-common-props.yaml.

Backward compatibility is maintained by reading the legacy boolean
properties first and passing them as the default_pol argument to
phy_get_rx/tx_polarity(). If the standard properties are absent the
legacy values are used transparently, so existing device trees remain
functional without modification.

Link: https://git.kernel.org/linus/66d8a334b57e64e43810623b3d88f0ce9745270b
Signed-off-by: Lucien.Jheng <lucienzx159@gmail.com>