u-boot.git/drivers/net, branch v2012.10

da850/omap-l138: davinci_emac: Suppress auto negotiation if needed

2012-10-01T17:02:13+00:00

negotiation is enabled in RMII mode. Some boards based on da850 need
to suppress this procedure.

CC: Rajashekhara, Sudhakar 
CC: Lad, Prabhakar 
CC: Hadli, Manjunath 
CC: sbabic@denx.de
Acked-by: Stefano Babic 
CC: Tom Rini 
Signed-off-by: Bastian Ruppert 
Acked-by: Prabhakar Lad

Merge branch 'master' of git://git.denx.de/u-boot-net

2012-09-27T19:06:07+00:00

FEC: Replace magic contants

2012-09-27T17:22:10+00:00

Replace the magic contant 1 << 24 with properly defined bits.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Fabio Estevam 
Cc: Otavio Salvador 
Cc: Stefano Babic

FEC: Rework the TX wait mechanism

2012-09-27T17:22:10+00:00

The mechanism waiting for transmission to finish in fec_send() now
relies on the E-bit being cleared in the TX buffer descriptor. In
case of data cache being on, this means invalidation of data cache
above this TX buffer descriptor on each test for the E-bit being
cleared.

Apparently, there is another way to check if the transmission did
complete. This is by checking the TDAR bit in the X_DES_ACTIVE
register. Reading a register does not need any data cache invalidation,
which is beneficial.

Rework the sequence that wait for completion of the transmission so that
the TDAR bit is tested first and afterwards check the E-bit being clear.
This cuts down the number of cache invalidation calls to one.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Fabio Estevam 
Cc: Otavio Salvador 
Cc: Stefano Babic

FEC: Remove endless loop in the FEC driver

2012-09-27T17:22:09+00:00

The FEC hardware sometimes errors out on data transfer and hangs in
the tightloop adjusted by this patch. So add timeout into the tightloop
to make such a hang recoverable.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Fabio Estevam 
Cc: Otavio Salvador 
Cc: Stefano Babic

FEC: Properly align address over the buffers for cache ops

2012-09-27T17:22:09+00:00

Align the address that's to be invalidated/flushed properly.

Signed-off-by: Marek Vasut 
Cc: Benoit Thebaudeau 
Cc: Eric Nelson 
Cc: Fabio Estevam 
Cc: Joe Hershberger

FEC: Do not pass unaligned buffer to network stack

2012-09-27T17:22:09+00:00

Do not pass unaligned RX buffer to the upper layers. The upper layer,
especially in the ARP case, recycles the buffer and passes it back into
the FEC, into it's TX path. With caches enabled, the FEC hangs on this
from time to time.

Signed-off-by: Marek Vasut 
Cc: Benoit Thebaudeau 
Cc: Eric Nelson 
Cc: Fabio Estevam 
Cc: Joe Hershberger 
Tested-by: Fabio Estevam

net: Add Vitesse VSC8662 PHY support

2012-09-27T17:21:59+00:00

-VSC8662 is Dual Port 10/100/1000Base-T Phy,
 100Base-FX/1000/Base-X Gigabit Ethernt Transceiver Phy.

-Its register set and features are similar to
 other Vitesse Phys

Signed-off-by: Priyanka Jain 
Signed-off-by: York Sun

net/phy: support the mv88e6352 switch

2012-09-27T17:21:56+00:00

This patch add support for the configuration of an external switch from
the 88E6xxx series from Marvell trough an MDIO link using indirect
adressing. This can be used if we do not want to use an EEPROM for the
configuration.

This driver is not generic and was not tested on other switches than the
88e6352. This is proposed as a first implementation that is somewhat
limited but works and that can be used as a basis for further
developments for this switch family.

Signed-off-by: Valentin Longchamp 
cc: Holger Brunck 
cc: Prafulla Wadaskar 
cc: Joe Hershberger

net: Add driver for Zynq Gem IP

2012-09-26T17:36:32+00:00

Device driver for Zynq Gem IP.

Signed-off-by: Michal Simek 
CC: Joe Hershberger 
CC: Marek Vasut 
Acked-by: Marek Vasut