<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/net, branch v2013.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board</title>
<updated>2012-11-28T00:28:06+00:00</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2012-10-23T09:40:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d31e53b42c35a9285c1e688733ceaa995689418b'/>
<id>d31e53b42c35a9285c1e688733ceaa995689418b</id>
<content type='text'>
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers/net/: sparse fixes</title>
<updated>2012-11-04T18:00:36+00:00</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2012-10-29T13:34:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=960d70c60055cbc4fbf4ce170959ecf2839bc788'/>
<id>960d70c60055cbc4fbf4ce170959ecf2839bc788</id>
<content type='text'>
phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static?
phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static?
phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static?
phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static?
phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static?
phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static?
phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta
vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static?
vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static?
tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static?
tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static?
tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static?
eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static?
p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static?

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static?
phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static?
phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static?
phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static?
phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static?
phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static?
phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta
vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static?
vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static?
tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static?
tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static?
tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static?
eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static?
p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static?

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net/: sparse fixes</title>
<updated>2012-11-04T18:00:36+00:00</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2012-10-29T13:34:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0637059088a2579b3c0d67a5ca7d34dd7721204f'/>
<id>0637059088a2579b3c0d67a5ca7d34dd7721204f</id>
<content type='text'>
bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static?
bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static?
bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static?
arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static?
arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static?
arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static?
atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static?
net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static?
net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static?
ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static?
ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static?
tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static?
tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static?
eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static?

Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020
"net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING
clause from when it was necessary to avoid warnings when it was embedded
in net.c.

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static?
bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static?
bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static?
arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static?
arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static?
arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static?
atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static?
net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static?
net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static?
ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static?
ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static?
tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static?
tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static?
eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static?

Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020
"net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING
clause from when it was necessary to avoid warnings when it was embedded
in net.c.

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>include/linux/byteorder: import latest endian definitions from linux</title>
<updated>2012-11-04T18:00:34+00:00</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2012-10-29T13:34:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=eef1cf2d5cf1cae5fb76713e912263dedf110aeb'/>
<id>eef1cf2d5cf1cae5fb76713e912263dedf110aeb</id>
<content type='text'>
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives.  Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h.  They come with 'const' added for some swab functions, so
fix those up, too:

include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]

Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).

We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:

macb.c:54:0: warning: "barrier" redefined [enabled by default]

In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)).  This fixes
arch/powerpc/lib/bootm.c:

bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token

powerpc sparse builds yield:

include/common.h:356:22: error: marked inline, but without a definition

the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'

also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]

and:

Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here

and:

In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives.  Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h.  They come with 'const' added for some swab functions, so
fix those up, too:

include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]

Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).

We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:

macb.c:54:0: warning: "barrier" redefined [enabled by default]

In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)).  This fixes
arch/powerpc/lib/bootm.c:

bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token

powerpc sparse builds yield:

include/common.h:356:22: error: marked inline, but without a definition

the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'

also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]

and:

Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here

and:

In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: Remove support for NETARM</title>
<updated>2012-10-26T20:38:00+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2012-10-03T08:54:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b411eb30f5ccca861b5aeee6b8e5880d4e4aea6b'/>
<id>b411eb30f5ccca861b5aeee6b8e5880d4e4aea6b</id>
<content type='text'>
This stuff has been rotting in the tree for a while now. Remove it.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This stuff has been rotting in the tree for a while now. Remove it.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/fm: fix TBI PHY address settings</title>
<updated>2012-10-22T20:52:46+00:00</updated>
<author>
<name>shaohui xie</name>
<email>Shaohui.Xie@freescale.com</email>
</author>
<published>2012-10-11T20:25:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1f3bd3e239fb0542128f7c911829c9f0360b0d8f'/>
<id>1f3bd3e239fb0542128f7c911829c9f0360b0d8f</id>
<content type='text'>
TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is wrong in case of FM2, which has a different
mac base.

struct dtsec *regs = (struct dtsec *)fm_eth-&gt;mac-&gt;base;
/* Assign a Physical address to the TBI */
out_be32(&amp;regs-&gt;tbipa, CONFIG_SYS_TBIPA_VALUE);

Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is wrong in case of FM2, which has a different
mac base.

struct dtsec *regs = (struct dtsec *)fm_eth-&gt;mac-&gt;base;
/* Assign a Physical address to the TBI */
out_be32(&amp;regs-&gt;tbipa, CONFIG_SYS_TBIPA_VALUE);

Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fm/mEMAC: add mEMAC frame work</title>
<updated>2012-10-22T19:31:25+00:00</updated>
<author>
<name>Roy Zang</name>
<email>tie-fei.zang@freescale.com</email>
</author>
<published>2012-10-08T07:44:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=111fd19e3b9eb1005fd24ef09c163dd10103f5fa'/>
<id>111fd19e3b9eb1005fd24ef09c163dd10103f5fa</id>
<content type='text'>
The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.

Signed-off-by: Sandeep Singh &lt;Sandeep@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.

Signed-off-by: Sandeep Singh &lt;Sandeep@freescale.com&gt;
Signed-off-by: Poonam Aggrwal &lt;poonam.aggrwal@freescale.com&gt;
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Add B4860 and variant SoCs</title>
<updated>2012-10-22T19:31:24+00:00</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2012-10-08T07:44:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d2404141f9cb45a01da3297bb873510799351a60'/>
<id>d2404141f9cb45a01da3297bb873510799351a60</id>
<content type='text'>
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
    clusters-each core runs up to 1.2 GHz, with an architecture highly
    optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
    cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
    each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
    including Turbo or Viterbi decoding, Turbo encoding and rate matching,
    MIMO MMSE equalization scheme, matrix operations, CRC insertion and
    check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
    and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
    the e6500 cores, SC3900 FVP cores, memories and external interfaces.
    CoreNet fabric interconnect runs at 667 MHz and supports coherent and
    non-coherent out of order transactions with prioritization and
    bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
  Frame Manager (FMan), which supports in-line packet parsing and general
    classification to enable policing and QoS-based packet distribution
  Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
    of queue management, task management, load distribution, flow ordering,
    buffer management, and allocation tasks from the cores
  Security engine (SEC 5.3)-crypto-acceleration for protocols such as
    IPsec, SSL, and 802.16
  RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
    outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
    bandwidth saving and high utilization of processor elements. The
    9856-Kbyte internal memory space includes the following:
  32 Kbyte L1 ICache per e6500/SC3900 core
  32 Kbyte L1 DCache per e6500/SC3900 core
  2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  2048 Kbyte unified L2 cache for the e6500 cluster
  Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
  Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
    of up to 8 lanes
  Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
    less antenna connection
  Two 10-Gbit Ethernet controllers (10GEC)
  Six 1G/2.5-Gbit Ethernet controllers for network communications
  PCI Express controller
  Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
    clusters-each core runs up to 1.2 GHz, with an architecture highly
    optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
    cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
    each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
    including Turbo or Viterbi decoding, Turbo encoding and rate matching,
    MIMO MMSE equalization scheme, matrix operations, CRC insertion and
    check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
    and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
    the e6500 cores, SC3900 FVP cores, memories and external interfaces.
    CoreNet fabric interconnect runs at 667 MHz and supports coherent and
    non-coherent out of order transactions with prioritization and
    bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
  Frame Manager (FMan), which supports in-line packet parsing and general
    classification to enable policing and QoS-based packet distribution
  Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
    of queue management, task management, load distribution, flow ordering,
    buffer management, and allocation tasks from the cores
  Security engine (SEC 5.3)-crypto-acceleration for protocols such as
    IPsec, SSL, and 802.16
  RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
    outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
    bandwidth saving and high utilization of processor elements. The
    9856-Kbyte internal memory space includes the following:
  32 Kbyte L1 ICache per e6500/SC3900 core
  32 Kbyte L1 DCache per e6500/SC3900 core
  2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  2048 Kbyte unified L2 cache for the e6500 cluster
  Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
  Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
    of up to 8 lanes
  Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
    less antenna connection
  Two 10-Gbit Ethernet controllers (10GEC)
  Six 1G/2.5-Gbit Ethernet controllers for network communications
  PCI Express controller
  Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Add T4240 SoC</title>
<updated>2012-10-22T19:31:23+00:00</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2012-10-08T07:44:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9e758758491b0d7a71bdf1db8cd860b599d7e657'/>
<id>9e758758491b0d7a71bdf1db8cd860b599d7e657</id>
<content type='text'>
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar@freescale.com&gt;
Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>m68k: net: Fix unused variable in mcfmii.c</title>
<updated>2012-10-19T15:47:41+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2012-10-03T13:28:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2b758cad8dfe8a04ed11340024d814612b912c3c'/>
<id>2b758cad8dfe8a04ed11340024d814612b912c3c</id>
<content type='text'>
The following warning was produced, fix it:

mcfmii.c: In function 'mcffec_miiphy_write':
mcfmii.c:318:8: warning: variable 'rdreg' set but not used [-Wunused-but-set-variable]

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: "Jin Zhengxiong-R64188" &lt;R64188@freescale.com&gt;
Cc: Jason Jin &lt;jason.jin@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The following warning was produced, fix it:

mcfmii.c: In function 'mcffec_miiphy_write':
mcfmii.c:318:8: warning: variable 'rdreg' set but not used [-Wunused-but-set-variable]

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: "Jin Zhengxiong-R64188" &lt;R64188@freescale.com&gt;
Cc: Jason Jin &lt;jason.jin@freescale.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
