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<title>u-boot.git/drivers/net, branch v2013.07-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net?h=v2013.07-rc1</id>
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<updated>2013-06-08T12:35:10Z</updated>
<entry>
<title>Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'</title>
<updated>2013-06-08T12:35:10Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2013-06-08T12:35:10Z</published>
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<id>urn:sha1:10e167329b029890a4c704f094822da5f259b886</id>
<content type='text'>
Conflicts:
	drivers/serial/Makefile
</content>
</entry>
<entry>
<title>net: fec_mxc: Add support for Vybrid VF610</title>
<updated>2013-06-03T08:56:53Z</updated>
<author>
<name>Alison Wang</name>
<email>b18965@freescale.com</email>
</author>
<published>2013-05-27T22:55:43Z</published>
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<id>urn:sha1:bcb6e9023a119a1cbcaf8289576e5aa155331802</id>
<content type='text'>
This patch adds FEC support for Vybrid VF610 platform.

In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.

Signed-off-by: Alison Wang &lt;b18965@freescale.com&gt;
Reviewed-by: Benoit Thebaudeau &lt;benoit.thebaudeau@advansee.com&gt;
Reviewed-by: Benoît Thébaudeau &lt;benoit.thebaudeau@advansee.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'u-boot/master' into 'u-boot-arm/master'</title>
<updated>2013-05-30T12:45:06Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2013-05-30T12:45:06Z</published>
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<id>urn:sha1:a19b0dd62d7b8efc658fa1aa685ff5665878f3ee</id>
<content type='text'>
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
</content>
</entry>
<entry>
<title>Enable XAUI interface for B4860QDS</title>
<updated>2013-05-24T21:54:12Z</updated>
<author>
<name>Suresh Gupta</name>
<email>suresh.gupta@freescale.com</email>
</author>
<published>2013-03-25T07:40:13Z</published>
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<id>urn:sha1:16d88f415ab799287672ae6cd08bf3ce975de2b5</id>
<content type='text'>
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
	The PHY addresses of Teranetics PHY on XAUI riser card are assigned
	based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
	AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta &lt;suresh.gupta@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>net/phy: fix select line for TN80xx</title>
<updated>2013-05-24T21:54:09Z</updated>
<author>
<name>Shaohui Xie</name>
<email>Shaohui.Xie@freescale.com</email>
</author>
<published>2013-03-25T07:39:59Z</published>
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<id>urn:sha1:d54097b6c10aab68dd0a88ec0d5c86615d3dd597</id>
<content type='text'>
TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.

Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx</title>
<updated>2013-05-15T12:41:04Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2013-05-14T22:47:43Z</published>
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<id>urn:sha1:fb651b10d43be36e7d7e16704c4b5ea1e295587a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>smc911x: fix the timeout detection</title>
<updated>2013-05-15T12:41:03Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2013-05-08T21:42:44Z</published>
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<id>urn:sha1:bee0dc2fec422175f2f23e2ed35152b40788a055</id>
<content type='text'>
If timeout is occurred at the while loop above,
the value of 'timeout' is -1, not 0.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
</entry>
<entry>
<title>net/phy: add VSC8574 support</title>
<updated>2013-05-14T21:13:25Z</updated>
<author>
<name>Shaohui Xie</name>
<email>Shaohui.Xie@freescale.com</email>
</author>
<published>2013-03-25T07:39:31Z</published>
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<id>urn:sha1:7794b1a7e6bb7fd678f00b17feb15e5d392fb5b0</id>
<content type='text'>
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.

Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>net/fm: fixup ethernet for mEMAC</title>
<updated>2013-05-14T21:13:24Z</updated>
<author>
<name>Shengzhou Liu</name>
<email>Shengzhou.Liu@freescale.com</email>
</author>
<published>2013-03-25T07:39:29Z</published>
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<id>urn:sha1:ae8a5d10f34c8ab6421d5204956de18c9defbf1d</id>
<content type='text'>
- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
  MAC node disabled incorrectly.

Signed-off-by: Shengzhou Liu &lt;Shengzhou.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
<entry>
<title>powerpc/mpc85xx: Add T4160 SoC</title>
<updated>2013-05-14T21:00:29Z</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-03-25T07:33:29Z</published>
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<id>urn:sha1:b62408464b749b57c4ec83594e09fa78dbd6bca4</id>
<content type='text'>
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
</entry>
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