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<title>u-boot.git/drivers/net, branch v2014.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>armv8/fsl-lsch3: Add support to load and start MC Firmware</title>
<updated>2014-07-03T06:40:58+00:00</updated>
<author>
<name>J. German Rivera</name>
<email>German.Rivera@freescale.com</email>
</author>
<published>2014-06-23T22:15:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b940ca64b22ba8980fd4ec8dda028f6b1a2ed79d'/>
<id>b940ca64b22ba8980fd4ec8dda028f6b1a2ed79d</id>
<content type='text'>
Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.

Signed-off-by: J. German Rivera &lt;German.Rivera@freescale.com&gt;
Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Lijun Pan &lt;Lijun.Pan@freescale.com&gt;
Signed-off-by: Shruti Kanetkar &lt;Shruti@Freescale.com&gt;
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<pre>
Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.

Signed-off-by: J. German Rivera &lt;German.Rivera@freescale.com&gt;
Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
Signed-off-by: Lijun Pan &lt;Lijun.Pan@freescale.com&gt;
Signed-off-by: Shruti Kanetkar &lt;Shruti@Freescale.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Merge branch 'u-boot/master' into 'u-boot-arm/master'</title>
<updated>2014-06-25T08:39:58+00:00</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2014-06-25T08:39:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ed1d98d801dfb6384d0f2fff45ce1ebf884944ca'/>
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<pre>
</pre>
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</entry>
<entry>
<title>net: macb: enable dcache in macb</title>
<updated>2014-06-14T16:07:01+00:00</updated>
<author>
<name>Wu, Josh</name>
<email>Josh.wu@atmel.com</email>
</author>
<published>2014-05-27T08:31:05+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5ae0e38278ad3becfc9a0a6bfc5ab8c531ccd621'/>
<id>5ae0e38278ad3becfc9a0a6bfc5ab8c531ccd621</id>
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Add to code to flush the dcache after we writing in DMA buffer.
Also we need invalidate the dcache before we check the status in the
DMA buffer.

Tested in SAMA5D3x-EK with gmac0. Tftp download speed shows in below:
	Disable DCache: 1.1 MiB/s
	Enable DCache: 1.6 MiB/s
Increase speed with about 40%.

The code should have no impact with the boards which are not
enable_dcache().
Tested in AT91SAM9M10G45EK.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
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<pre>
Add to code to flush the dcache after we writing in DMA buffer.
Also we need invalidate the dcache before we check the status in the
DMA buffer.

Tested in SAMA5D3x-EK with gmac0. Tftp download speed shows in below:
	Disable DCache: 1.1 MiB/s
	Enable DCache: 1.6 MiB/s
Increase speed with about 40%.

The code should have no impact with the boards which are not
enable_dcache().
Tested in AT91SAM9M10G45EK.

Signed-off-by: Josh Wu &lt;josh.wu@atmel.com&gt;
Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>macb: make checkpatch clean</title>
<updated>2014-06-14T16:07:00+00:00</updated>
<author>
<name>Andreas Bießmann</name>
<email>andreas.devel@googlemail.com</email>
</author>
<published>2014-05-26T20:55:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ceef983bf9b687926b274ad0eee8aae5a1812c92'/>
<id>ceef983bf9b687926b274ad0eee8aae5a1812c92</id>
<content type='text'>
This also renames the CONFIG_SYS_MACB_xx defines. They are used just local and
therefore don't need the CONFIG_SYS_ prefix.

Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
Reviewed-by: Josh Wu &lt;josh.wu@atmel.com&gt;
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<pre>
This also renames the CONFIG_SYS_MACB_xx defines. They are used just local and
therefore don't need the CONFIG_SYS_ prefix.

Signed-off-by: Andreas Bießmann &lt;andreas.devel@googlemail.com&gt;
Reviewed-by: Josh Wu &lt;josh.wu@atmel.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>net: sh-eth: Fix typo from rESR_RTLF to EESR_RTLF</title>
<updated>2014-06-10T08:05:03+00:00</updated>
<author>
<name>Nobuhiro Iwamatsu</name>
<email>nobuhiro.iwamatsu.yj@renesas.com</email>
</author>
<published>2014-01-22T22:52:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1dbd7280dc73dd4a6b38f3d17426393951d7d53e'/>
<id>1dbd7280dc73dd4a6b38f3d17426393951d7d53e</id>
<content type='text'>
'r' of rESR_RTLF is a mistake of E.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro.iwamatsu.yj@renesas.com&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
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<pre>
'r' of rESR_RTLF is a mistake of E.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro.iwamatsu.yj@renesas.com&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: sh-eth: Fix coding style</title>
<updated>2014-06-10T08:05:03+00:00</updated>
<author>
<name>Nobuhiro Iwamatsu</name>
<email>nobuhiro.iwamatsu.yj@renesas.com</email>
</author>
<published>2014-01-22T22:52:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e2752db0520541d6c62401eb4acfc738c5d0b9db'/>
<id>e2752db0520541d6c62401eb4acfc738c5d0b9db</id>
<content type='text'>
This fixes checkpatch's warning.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro.iwamatsu.yj@renesas.com&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
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<pre>
This fixes checkpatch's warning.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro.iwamatsu.yj@renesas.com&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>net: sh-eth: Add support R7S72100 of rmobile</title>
<updated>2014-06-10T08:05:03+00:00</updated>
<author>
<name>Nobuhiro Iwamatsu</name>
<email>nobuhiro.iwamatsu.yj@renesas.com</email>
</author>
<published>2014-01-22T22:52:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=62cbddc493e5f4c6c1e1ba62bdf36f3df4708a16'/>
<id>62cbddc493e5f4c6c1e1ba62bdf36f3df4708a16</id>
<content type='text'>
The R7S72100 of ARM SoC that Renesas manufactured has one Ether port.
This has the same IP SH-Ether. This patch adds support of the R7S72100
in SH-Ether.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro.iwamatsu.yj@renesas.com&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
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<pre>
The R7S72100 of ARM SoC that Renesas manufactured has one Ether port.
This has the same IP SH-Ether. This patch adds support of the R7S72100
in SH-Ether.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro.iwamatsu.yj@renesas.com&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>phy: fix create_phy_by_mask for when its given an actual search mask</title>
<updated>2014-06-05T18:44:56+00:00</updated>
<author>
<name>Cormier, Jonathan</name>
<email>jcormier@criticallink.com</email>
</author>
<published>2014-05-21T17:08:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=08be2836df0b07aac65fea583b762335569fd47a'/>
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<content type='text'>
get_phy_id returns -EIO when it can't read from a phy at a given addr.  This would cause
create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask.

Example usage:
Replace
    phydev = phy_connect(bus, phy_addr, dev, phy_if)
with
    phydev = phy_find_by_mask(bus, phy_mask, phy_if)
    if (phydev)
	phy_connect_dev(phydev, dev);

Signed-off-by: Cormier, Jonathan &lt;jcormier@criticallink.com&gt;
Cc: Joe Hershberger &lt;joe.hershberger@gmail.com&gt;
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<pre>
get_phy_id returns -EIO when it can't read from a phy at a given addr.  This would cause
create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask.

Example usage:
Replace
    phydev = phy_connect(bus, phy_addr, dev, phy_if)
with
    phydev = phy_find_by_mask(bus, phy_mask, phy_if)
    if (phydev)
	phy_connect_dev(phydev, dev);

Signed-off-by: Cormier, Jonathan &lt;jcormier@criticallink.com&gt;
Cc: Joe Hershberger &lt;joe.hershberger@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net/designware: Make DMA burst length configurable and reduce by default</title>
<updated>2014-05-25T15:23:58+00:00</updated>
<author>
<name>Ian Campbell</name>
<email>ijc@hellion.org.uk</email>
</author>
<published>2014-05-08T21:26:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=49692c5f517d8e44ed9db0de778728fe7d2a300c'/>
<id>49692c5f517d8e44ed9db0de778728fe7d2a300c</id>
<content type='text'>
The correct value for this setting can vary across SoCs and boards, so make it
configurable.

Also reduce the default value to 8, which is the same default as used in the
Linux driver.

Signed-off-by: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
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<pre>
The correct value for this setting can vary across SoCs and boards, so make it
configurable.

Also reduce the default value to 8, which is the same default as used in the
Linux driver.

Signed-off-by: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net/designware: reorder struct dw_eth_dev to pack more efficiently.</title>
<updated>2014-05-25T15:23:48+00:00</updated>
<author>
<name>Ian Campbell</name>
<email>ijc@hellion.org.uk</email>
</author>
<published>2014-05-14T18:30:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1857075a7f00ff0a62b13170a78c70ff94e30f96'/>
<id>1857075a7f00ff0a62b13170a78c70ff94e30f96</id>
<content type='text'>
On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote:
&gt; The {r,t}xbuffs fields also need to be aligned. Previously this was done
&gt; implicitly because they immediately followed the descriptor tables. Make this
&gt; explicit and also move to the head of the struct.

Looks like I managed to not actually commit the move of the field to the
head of the struct! v3.1 follows....

Ian.

8&lt;------------

&gt;From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001
From: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Date: Thu, 1 May 2014 19:45:15 +0100
Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more
 efficiently.

The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could
be 256 or even larger. That means there is a potentially huge hole in the
struct before those fields, so move them to the front where they are better
packed.

Moving them to the front also helps ensure that so long as dw_eth_dev is
properly aligned (which it is since "net/designware: ensure device private data
is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids
having to worry too much about compiler specifics.

The {r,t}xbuffs fields also need to be aligned. Previously this was done
implicitly because they immediately followed the descriptor tables. Make this
explicit and also move to the head of the struct.

Signed-off-by: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
Tested-by: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
Reviewed-by: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
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<pre>
On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote:
&gt; The {r,t}xbuffs fields also need to be aligned. Previously this was done
&gt; implicitly because they immediately followed the descriptor tables. Make this
&gt; explicit and also move to the head of the struct.

Looks like I managed to not actually commit the move of the field to the
head of the struct! v3.1 follows....

Ian.

8&lt;------------

&gt;From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001
From: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Date: Thu, 1 May 2014 19:45:15 +0100
Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more
 efficiently.

The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could
be 256 or even larger. That means there is a potentially huge hole in the
struct before those fields, so move them to the front where they are better
packed.

Moving them to the front also helps ensure that so long as dw_eth_dev is
properly aligned (which it is since "net/designware: ensure device private data
is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids
having to worry too much about compiler specifics.

The {r,t}xbuffs fields also need to be aligned. Previously this was done
implicitly because they immediately followed the descriptor tables. Make this
explicit and also move to the head of the struct.

Signed-off-by: Ian Campbell &lt;ijc@hellion.org.uk&gt;
Cc: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
Tested-by: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
Reviewed-by: Siarhei Siamashka &lt;siarhei.siamashka@gmail.com&gt;
</pre>
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</entry>
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