u-boot.git/drivers/net, branch v2014.07-rc4

net: sh-eth: Fix typo from rESR_RTLF to EESR_RTLF

2014-06-10T08:05:03Z

'r' of rESR_RTLF is a mistake of E. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu

net: sh-eth: Fix coding style

2014-06-10T08:05:03Z

This fixes checkpatch's warning. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu

net: sh-eth: Add support R7S72100 of rmobile

2014-06-10T08:05:03Z

The R7S72100 of ARM SoC that Renesas manufactured has one Ether port. This has the same IP SH-Ether. This patch adds support of the R7S72100 in SH-Ether. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu

phy: fix create_phy_by_mask for when its given an actual search mask

2014-06-05T18:44:56Z

get_phy_id returns -EIO when it can't read from a phy at a given addr. This would cause create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask. Example usage: Replace phydev = phy_connect(bus, phy_addr, dev, phy_if) with phydev = phy_find_by_mask(bus, phy_mask, phy_if) if (phydev) phy_connect_dev(phydev, dev); Signed-off-by: Cormier, Jonathan Cc: Joe Hershberger

net/designware: Make DMA burst length configurable and reduce by default

2014-05-25T15:23:58Z

The correct value for this setting can vary across SoCs and boards, so make it configurable. Also reduce the default value to 8, which is the same default as used in the Linux driver. Signed-off-by: Ian Campbell Cc: Alexey Brodkin

net/designware: reorder struct dw_eth_dev to pack more efficiently.

2014-05-25T15:23:48Z

On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote: > The {r,t}xbuffs fields also need to be aligned. Previously this was done > implicitly because they immediately followed the descriptor tables. Make this > explicit and also move to the head of the struct. Looks like I managed to not actually commit the move of the field to the head of the struct! v3.1 follows.... Ian. 8<------------ >From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 1 May 2014 19:45:15 +0100 Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more efficiently. The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could be 256 or even larger. That means there is a potentially huge hole in the struct before those fields, so move them to the front where they are better packed. Moving them to the front also helps ensure that so long as dw_eth_dev is properly aligned (which it is since "net/designware: ensure device private data is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids having to worry too much about compiler specifics. The {r,t}xbuffs fields also need to be aligned. Previously this was done implicitly because they immediately followed the descriptor tables. Make this explicit and also move to the head of the struct. Signed-off-by: Ian Campbell Cc: Alexey Brodkin Tested-by: Siarhei Siamashka Reviewed-by: Siarhei Siamashka

net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGN

2014-05-25T15:23:15Z

This is required at least on ARM. When sending instead of simply invalidating the entire descriptor, flush as little as possible while still respecting ARCH_DMA_MINALIGN, as requested by Alexey. Signed-off-by: Ian Campbell Cc: Alexey Brodkin

net/designware: ensure device private data is DMA aligned.

2014-05-25T15:23:12Z

struct dw_eth_dev contains fields which are accessed via DMA, so make sure it is aligned to a dma boundary. Without this I see: ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0 Signed-off-by: Ian Campbell Reviewed-by: Alexey Brodkin Acked-by: Marek Vasut

net: phy/vitesse: Add support for VSC8664 phy module

2014-05-16T21:24:05Z

This patch adds support for VSC8664 PHY module which can be found on Freescale's T4240RDB boards. Signed-off-by: Chunhe Lan Reviewed-by: York Sun

powerpc/85xx: add T4080 SoC support

2014-05-13T15:26:54Z

The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu