u-boot.git/drivers/net, branch v2015.10-rc2

arm: mvebu: Enable NAND controller on MVEBU SoC's

2015-08-17T16:49:02Z

This patch enables the NAND controller on the Armada XP/38x and provides a new function that returns the NAND controller input clock. This function will be used by the MVEBU NAND driver. As part of this patch, the multiple BIT macro definitions are moved to a common place in soc.h. Signed-off-by: Stefan Roese Cc: Peter Morrow Cc: Luka Perkov

net: lpc32xx: eth buffers base config

2015-08-13T11:19:41Z

Add support to specify the Ethernet buffer base address; if none are supply by the board, the default value is use (from existing code). Signed-off-by: Sylvain Lemieux Acked-by: Joe Hershberger

net: e1000: Increase autoneg timeout to 8 seconds

2015-08-12T19:15:29Z

The current 4.5 timeout for the autonegotiation are not enough to complete it on my platform. Using the Intel E1000 PCIe card in the Marvell db-mv784mp-gp eval board. So lets increase the timeout to 8 seconds. Signed-off-by: Stefan Roese Cc: Joe Hershberger Cc: Simon Glass

net: phy: broadcom: Add BCM Cygnus PHY

2015-08-11T18:49:17Z

Add Ethernet PHY for BCM Cygnus SoC Signed-off-by: Jiandong Zheng Signed-off-by: Steve Rae Acked-by: Joe Hershberger

net: phy: delay only if reset handler is registered

2015-08-11T18:48:25Z

With commit e3a77218a256edbe201112a39beeed8adcabae3f the MII bus is only reset if a reset handler is registered. If there is no reset handler there is no need to wait for a device to come out of the reset. Signed-off-by: Jörg Krause

net: phy: fix data type of phy_id

2015-08-11T18:47:15Z

phy_id is declared as u32 in create_phy_by_mask and in struct phy_device. Signed-off-by: Jörg Krause

qoriq eth.c bugfix: handle received corrupted frames correctly

2015-08-11T18:46:16Z

The rxbd is not correctly handled in case of a frame physical error (FPE) or frame size error (FSE). The rxbd must be cleared and advanced in case of an error to avoid receive stall. Signed-off-by: Daniel Inderbitzin

net: lpc32xx: add RMII phy mode support

2015-08-11T18:43:04Z

LPC32xx MAC and clock control configuration requires some minor quirks to deal with a phy connected by RMII. It's worth to mention that the kernel and legacy BSP from NXP sets SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011 and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also in my tests an SMSC LAN8700 phy device connected over RMII seems to work correctly without touching this bit. Add support of RMII, if CONFIG_RMII is defined, this option is aligned with a number of boards, which already define the same config value. Signed-off-by: Vladimir Zapolskiy Tested-by: Sylvain Lemieux

net: lpc32xx: improve MAC configuration on reset and initialization

2015-08-11T18:42:34Z

This change rearranges general MAC configuration and PHY specific configuration of MAC registers (duplex mode and speed), before this change set bits related to PHY configuration in MAC2 and COMMAND registers are rewritten by the following writing to the registers. Without the change auto negotiation on boot quite often is not completed in reasonable time: Waiting for PHY auto negotiation to complete......... TIMEOUT ! Additionally MAC1_SOFT_RESET clear bit is removed since it is done in preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead added missing MCFG_RESET_MII_MGMT on device initialization. Signed-off-by: Vladimir Zapolskiy

net: lpc32xx: connect MAC to phy with CONFIG_PHY_ADDR id

2015-08-11T18:38:51Z

The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX MAC to some specified phy by phy id, by chance the single user of lpc32xx_eth has CONFIG_PHY_ADDR set to 0, however other boards may have non-zero CONFIG_PHY_ADDR value, fix it. Signed-off-by: Vladimir Zapolskiy Acked-by: Albert ARIBAUD (3ADEV) Acked-by: Joe Hershberger