u-boot.git/drivers/net, branch v2016.03

net: phy: atheros: Fix problem with phy_reset() clearing BMCR

2016-02-26T19:32:37+00:00

In commit  [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION)
is cleared too. It causes auto-negotiation timeout error on Atheros's
PHY AR8033.

To fix this problem, genphy_config_aneg() and genphy_restart_aneg()
needs to be called in ar8035_config() to enable and restart
auto-negotiation.

Signed-off-by: Alison Wang 
Acked-by: Stefan Agner 
Acked-by: Joe Hershberger

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

2016-02-24T23:44:15+00:00

driver/fm: fdt.c: fix fdt_fixup_fman_firmware() to support ARM platforms

2016-02-24T16:51:13+00:00

Use fdt32_to_cpu() to convert the data correctly for both endianness
platforms.

Signed-off-by: Gong Qianyu 
Reviewed-by: York Sun

fm: fdt: Move fman ucode fixup to driver code

2016-02-24T16:51:13+00:00

Not only powerpc/mpc85xx but also Freescale Layerscape platforms will
use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device
tree. So move the function to Fman driver code.

Signed-off-by: Gong Qianyu 
Reviewed-by: York Sun

qe: move drivers/qe/qe.h to include/fsl_qe.h

2016-02-24T16:51:13+00:00

As the QE firmware struct is shared with Fman, move the header file
out of drivers/qe/.

Signed-off-by: Gong Qianyu 
Reviewed-by: York Sun

net: phy: realtek: Use generic genphy_parse_link() for RTL8211E

2016-02-22T15:37:50+00:00

The problem with current implementation is that SPDDONE bit is 1
but link bit is zero. That's why phydev->link is setup to 0
which ending up in driver failure that link is not up.

Log:
Zynq> dhcp
ethernet@e000b000 Waiting for PHY auto negotiation to complete.......
done
ethernet@e000b000: No link.

There is at least 1ms delay between spddone bit and link up.

Use genphy_read_status() instead of realtek implemenation which is
working with page 11. Linux driver is also using generic implementation.

Signed-off-by: Michal Simek 
Signed-off-by: Michal Simek

Merge branch 'master' of git://git.denx.de/u-boot-atmel

2016-02-20T22:32:48+00:00

drivers: at91: clean up peripheral clock code

2016-02-18T20:34:40+00:00

Due to introducing the new peripheral clock handle functions,
use these functions to reduce the duplicated code.

Signed-off-by: Wenyou Yang 
Tested-by: Heiko Schocher 
[fixup for missing clk.h in at91_emac.c]
Signed-off-by: Andreas Bießmann

net: phy: marvell: Fix problem with phy_reset() clearing BMCR

2016-02-18T17:32:03+00:00

With commit a058052c [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Resulting in bit 12
being cleared (A/N enable). This leads to autonegotiation link problems,
at least on the Marvell Armada ClearFog board. I suspect that other
boards using this driver will be affected as well.

At the of m88e1111s_config(), phy_reset() is called. This is not needed
for the PHY to load the changed configuration, as phy_reset() is called
a few lines before already. So lets call genphy_restart_aneg() here
instead to start the AN correctly.

Tested on clearfog.

Signed-off-by: Stefan Roese 
Cc: Stefan Agner 
Cc: Hao Zhang 
Cc: Michal Simek 
Cc: Andy Fleming 
Cc: Joe Hershberger 
Acked-by: Joe Hershberger

net: phy: marvell: Call phy_reset() where possible

2016-02-18T17:32:00+00:00

Instead of coding the soft PHY reset function multiple times in marvell.c,
lets call the common phy_reset() function from phy.c.

Signed-off-by: Stefan Roese 
Cc: Stefan Agner 
Cc: Hao Zhang 
Cc: Michal Simek 
Cc: Andy Fleming 
Cc: Joe Hershberger 
Acked-by: Joe Hershberger