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<title>u-boot.git/drivers/net, branch v2016.11-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net?h=v2016.11-rc1</id>
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<updated>2016-10-02T00:05:14Z</updated>
<entry>
<title>net, macb: fix misaligned cache operation warning</title>
<updated>2016-10-02T00:05:14Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2016-08-29T05:46:11Z</published>
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<id>urn:sha1:592a749527d8c1d52d46e0cf2f04e72a2e05e5fb</id>
<content type='text'>
when using tftp on the smartweb board, it prints a lot of

CACHE: Misaligned operation at range [23b2e000, 23b2e100]

warnings ... fixed them.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvneta: Add support for Armada 3700 SoC</title>
<updated>2016-09-27T15:29:52Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2016-05-19T15:46:36Z</published>
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<id>urn:sha1:544eefe084661d5ee486aca0cd0ec03801bfced9</id>
<content type='text'>
This patch adds support for the Armada 3700 SoC to the Marvell mvneta
network driver.

Not like A380, in Armada3700, there are two layers of decode windows for GBE:
First layer is:  GbE Address window that resides inside the GBE unit,
Second layer is: Fabric address window which is located in the NIC400
                 (South Fabric).
To simplify the address decode configuration for Armada3700, we bypass the
first layer of GBE decode window by setting the first window to 4GB.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Cc: Wilson Ding &lt;dingwei@marvell.com&gt;
Cc: Victor Gu &lt;xigu@marvell.com&gt;
Cc: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Terry Zhou &lt;bjzhou@marvell.com&gt;
Cc: Hanna Hawa &lt;hannah@marvell.com&gt;
Cc: Haim Boot &lt;hayim@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>net: mvneta: Make driver 64bit safe</title>
<updated>2016-09-27T15:29:52Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2016-05-19T16:09:17Z</published>
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<id>urn:sha1:3cbc11da866936c04ef95ea077e891d907cd4ad9</id>
<content type='text'>
The mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This
patch fixes the compilation warnings seen on this 64bit platform.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Cc: Wilson Ding &lt;dingwei@marvell.com&gt;
Cc: Victor Gu &lt;xigu@marvell.com&gt;
Cc: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Terry Zhou &lt;bjzhou@marvell.com&gt;
Cc: Hanna Hawa &lt;hannah@marvell.com&gt;
Cc: Haim Boot &lt;hayim@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>net: mvneta: Round up top tx buffer boundaries for dcache ops</title>
<updated>2016-09-27T15:29:46Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2016-08-25T10:56:50Z</published>
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<id>urn:sha1:35e3fca7e3ddaa2ae1fe9bd00b22be73e60a6042</id>
<content type='text'>
check_cache_range() warns that the top boundaries are not properly
aligned when flushing or invalidating the buffers and make these
operations fail.

This gets rid of the warnings:
CACHE: Misaligned operation at range ...

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2016-09-26T21:10:56Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-09-26T17:24:46Z</published>
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<id>urn:sha1:cbe7706ab8aab06c18edaa9b120371f9c8012728</id>
<content type='text'>
trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046A</title>
<updated>2016-09-26T15:53:07Z</updated>
<author>
<name>York Sun</name>
<email>york.sun@nxp.com</email>
</author>
<published>2016-09-26T15:09:24Z</published>
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<id>urn:sha1:da28e58a7fc169625334b1e40f72067b481b352a</id>
<content type='text'>
Move this option to Kconfig and clean up existing uses.

Signed-off-by: York Sun &lt;york.sun@nxp.com&gt;
CC: Mingkai Hu &lt;mingkai.hu@nxp.com&gt;
CC: Gong Qianyu &lt;Qianyu.Gong@nxp.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>treewide: replace #include &lt;asm-generic/errno.h&gt; with &lt;linux/errno.h&gt;</title>
<updated>2016-09-24T02:25:27Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-09-21T02:28:57Z</published>
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<id>urn:sha1:5d97dff0424e3ae5c4325a04e662a6b60b8deb67</id>
<content type='text'>
Now, include/linux/errno.h is a wrapper of &lt;asm-generic/errno.h&gt;.
Replace all include directives for &lt;asm-generic/errno.h&gt; with
&lt;linux/errno.h&gt;.

&lt;asm-generic/...&gt; is supposed to be included from &lt;asm/...&gt; when
arch-headers fall back into generic implementation. Generally, they
should not be directly included from .c files.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
[trini: Add drivers/usb/host/xhci-rockchip.c]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>treewide: replace #include &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;</title>
<updated>2016-09-23T21:55:42Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-09-21T02:28:55Z</published>
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<id>urn:sha1:1221ce459d04a428f8880f58581f671b736c3c27</id>
<content type='text'>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap &lt;asm-generic/errno.h&gt;)

Replace all include directives for &lt;asm/errno.h&gt; with &lt;linux/errno.h&gt;.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>net: pch_gbe: Make 64 bit safe</title>
<updated>2016-09-21T13:04:32Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-09-08T06:47:34Z</published>
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<id>urn:sha1:96cb57c5ea1905c05435b42ac378938971b83766</id>
<content type='text'>
The pch_gbe driver previously casted pointers to &amp; from unsigned 32 bit
integers in many locations. This breaks the driver on 64 bit systems,
producing streams of compiler warnings about mismatched pointer &amp;
integer sizes and then failing to keep track of addresses correctly at
runtime.

Fix the driver for 64 bit systems by using unsigned longs in place of
the previously used 32 bit integers.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>net: pch_gbe: Use dm_pci_map_bar to discover MMIO base</title>
<updated>2016-09-21T13:04:32Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-09-08T06:47:33Z</published>
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<id>urn:sha1:154bf12f78c012895e7b42f844b7b92c4f015509</id>
<content type='text'>
Reading the PCI BAR &amp; converting the result to a physical address is not
safe across all architectures. For example on MIPS the virtual:physical
mapping is not 1:1, so we cannot directly make use of the physical
address.

Use the more generic BAR-mapping function dm_pci_map_bar to discover the
MMIO base address, which should work across architectures.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
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