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<title>u-boot.git/drivers/net, branch v2017.11-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net?h=v2017.11-rc1</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/net?h=v2017.11-rc1'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2017-09-26T04:51:30Z</updated>
<entry>
<title>ARM: mvebu: Convert CONFIG_MVNETA to Kconfig</title>
<updated>2017-09-26T04:51:30Z</updated>
<author>
<name>Chris Packham</name>
<email>judge.packham@gmail.com</email>
</author>
<published>2017-08-21T08:17:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7654f62f4e84c40e0f604f23126fc794ae843da1'/>
<id>urn:sha1:7654f62f4e84c40e0f604f23126fc794ae843da1</id>
<content type='text'>
This converts the following to Kconfig:
   CONFIG_MVNETA

Signed-off-by: Chris Packham &lt;judge.packham@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>nds32: ftmac100: Fix write mac addr fail problem.</title>
<updated>2017-09-21T02:30:22Z</updated>
<author>
<name>rick</name>
<email>rick@andestech.com</email>
</author>
<published>2017-08-29T02:15:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1341494c7db46f4e4db59f7bb797c9ab79f4c51b'/>
<id>urn:sha1:1341494c7db46f4e4db59f7bb797c9ab79f4c51b</id>
<content type='text'>
After soft reset complete, write mac address immediately will fail.
Add delay to work around this problem.

Signed-off-by: rick &lt;rick@andestech.com&gt;
</content>
</entry>
<entry>
<title>nds32: ftmac100: support cache enable.</title>
<updated>2017-09-21T02:30:22Z</updated>
<author>
<name>rick</name>
<email>rick@andestech.com</email>
</author>
<published>2017-08-29T02:09:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ce4e2370f70f4bbd79e553dca73ec4439bfd567e'/>
<id>urn:sha1:ce4e2370f70f4bbd79e553dca73ec4439bfd567e</id>
<content type='text'>
Add cache inval and flush when rx and tx.

Signed-off-by: rick &lt;rick@andestech.com&gt;
</content>
</entry>
<entry>
<title>net: phy: micrel: Convert to livetree</title>
<updated>2017-09-18T18:40:34Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-09-11T20:04:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b343837e90bf7eb1b7b7b5117cd6e101b72bda10'/>
<id>urn:sha1:b343837e90bf7eb1b7b7b5117cd6e101b72bda10</id>
<content type='text'>
Update the Micrel KSZ90x1 driver for a live tree.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>net: designware: Convert to livetree</title>
<updated>2017-09-18T18:40:34Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-09-11T20:04:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=15050f1cb023052a5ab03d39e55119e9c6ce3eaf'/>
<id>urn:sha1:15050f1cb023052a5ab03d39e55119e9c6ce3eaf</id>
<content type='text'>
Update the Designware Ethernet MAC driver to support a live device
tree.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>blk: Remove various places that do flush cache after read</title>
<updated>2017-09-15T12:05:10Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-09-13T02:00:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=723b43daec7ee2ddb600cfcb9b0253d4a71c3915'/>
<id>urn:sha1:723b43daec7ee2ddb600cfcb9b0253d4a71c3915</id>
<content type='text'>
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.

The underlying drivers should be responsible for the cache operation.
Remove these codes completely.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
Reviewed-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: fsl-layerscape: Support to add RGMII for ls1088aqds</title>
<updated>2017-09-11T15:01:05Z</updated>
<author>
<name>Ashish Kumar</name>
<email>Ashish.Kumar@nxp.com</email>
</author>
<published>2017-08-31T11:07:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=17d066fc5db1a6f137e5b3113d918e14b1bd0230'/>
<id>urn:sha1:17d066fc5db1a6f137e5b3113d918e14b1bd0230</id>
<content type='text'>
This patch adds support for RGMII protocol

NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.

Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Signed-off-by: Amrita Kumari &lt;amrita.kumari@nxp.com&gt;
Signed-off-by: Ashish Kumar &lt;Ashish.Kumar@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: ls1088a: Add NXP LS1088A SoC support</title>
<updated>2017-09-11T15:00:13Z</updated>
<author>
<name>Ashish Kumar</name>
<email>Ashish.Kumar@nxp.com</email>
</author>
<published>2017-08-31T10:42:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6d9b82d085ea810c7bb2ed5203522e45cc72c336'/>
<id>urn:sha1:6d9b82d085ea810c7bb2ed5203522e45cc72c336</id>
<content type='text'>
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

Signed-off-by: Alison Wang &lt;alison.wang@nxp.com&gt;
Signed-off-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Signed-off-by: Ashish Kumar &lt;Ashish.Kumar@nxp.com&gt;
Signed-off-by: Raghav Dogra &lt;raghav.dogra@nxp.com&gt;
Signed-off-by: Shaohui Xie &lt;Shaohui.Xie@nxp.com&gt;
[YS: Revised commit message]
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>drivers:net:fsl-mc: Update MC address calculation</title>
<updated>2017-09-11T14:55:36Z</updated>
<author>
<name>Priyanka Jain</name>
<email>priyanka.jain@nxp.com</email>
</author>
<published>2017-08-24T11:12:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=033c538e567aca5f0876f2504b5e278c2a0f83a8'/>
<id>urn:sha1:033c538e567aca5f0876f2504b5e278c2a0f83a8</id>
<content type='text'>
Update MC address calculation as per MC design requirement of address
as least significant 512MB address of MC private allocated memory,
i.e. address should point to end address masked with 512MB offset in
private DRAM block.

Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Signed-off-by: Ashish Kumar &lt;ashish.kumar@nxp.com&gt;
[YS: reformatted commit message]
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>net: fix typos</title>
<updated>2017-09-07T18:23:52Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2017-08-29T16:44:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e4691564ccd366618934e70b7f621df7e1c5d70b'/>
<id>urn:sha1:e4691564ccd366618934e70b7f621df7e1c5d70b</id>
<content type='text'>
%s/Desriptor/Descriptor/g

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
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