Functions can return NULL in case of error that's why checking return
value is needed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

In case of phyread()/phy_setup_op() timeout code is working with
uninitialized phyreg variable. Initialize this variable to make sure
that code it not working with random value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

wait_for_bit_le32 returns negative value on failure. Fix phy...() to
handle these failures properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Combine repeated code from smi_reg_read/smi_reg_write into a common
function smi_wait_ready.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

On the SPEAr600 SoC, which has the dwmac1000 variant of the IP block,
the DMA reset never succeeds when a MII PHY is used (no problem with a
GMII PHY). The designware_eth_init() function sets the
DMAMAC_SRST bit in the DMA_BUS_MODE register, and then
polls until this bit clears. When a MII PHY is used, with the current
driver, this bit never clears and the driver therefore doesn't work.

The reason is that the PS bit of the GMAC_CONTROL register should be
correctly configured for the DMA reset to work. When the PS bit is 0,
it tells the MAC we have a GMII PHY, when the PS bit is 1, it tells
the MAC we have a MII PHY.

Doing a DMA reset clears all registers, so the PS bit is cleared as
well. This makes the DMA reset work fine with a GMII PHY. However,
with MII PHY, the PS bit should be set.

We have identified this issue thanks to two SPEAr600 platform:

- One equipped with a GMII PHY, with which the existing driver was
working fine.

- One equipped with a MII PHY, where the current driver fails because
the DMA reset times out.

Note: Taken from https://www.spinics.net/lists/netdev/msg432578.html

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

When connecting to from a CPU direct to a 88e6097 typically RGMII is
used. In order for traffic to actually pass we need to force the link up
so the CPU MAC on the other end will see the link.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

This makes sure the DMA buffers are properly aligned for the
hardware.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Add driver for Socionext AVE ethernet controller that includes MAC and
MDIO bus supporting RGMII/RMII modes.
The driver behaves the ethernet driver model (DM_ETH) with devicetree.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

VCAP tables must be initialized even if no advanced classification
is used. If no initialization is performed, then ECC error will
be observed by the user when the first packet enters the l2switch.
The error is marked in MPIC_EISR0 -bit 29 which means - Internal RAM
multi-bit ECC error.
This patch fixes the aforementioned ECC error by performing the
initialization of VCAP tables.

Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

If you send a final packet just before stopping the interface (e.g. a final
ACK as part of the UDP fastboot protocol), then that packet isn't reliably
delivered onto the wire.

Reap packets prior to stopping the interface to ensure any which are
in-flight make it out. Also remove buffer and len from the call to
cpdma_process() as we weren't using them on their return.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>