u-boot.git/drivers/net, branch v2018.09-rc2

fsl/mc: Limit the ethernet name to ETH_NAME_LEN

2018-08-08T15:23:49+00:00

The ethernet name should be within the ETH_NAME_LEN, as this
is the buffer space allocated to ethernet name.

Otherwise, this causes buffer overflow.

Reported-by: Ioana Ciornei 
Signed-off-by: Pankaj Bansal 
Reviewed-by: York Sun

net: zynq_gem: convert to use livetree

2018-07-26T19:08:23+00:00

This patch updates the zynq gem driver to support livetree.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Vipul Kumar 
Acked-by: Joe Hershberger

drivers: net: zynq_gem: fix phy dt node setting

2018-07-26T19:08:23+00:00

Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.

Signed-off-by: Grygorii Strashko 
Acked-by: Joe Hershberger 
Tested-by: Siva Durga Prasad Paladugu

drivers: net: cpsw: fix phy dt node setting

2018-07-26T19:08:23+00:00

Now CPSW driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.

Signed-off-by: Grygorii Strashko 
Acked-by: Joe Hershberger

net: phy: xilinx: switch to use phy_get_ofnode()

2018-07-26T19:08:22+00:00

Use PHY API phy_get_ofnode() helper to get PHY DT node.

Signed-off-by: Grygorii Strashko 
Acked-by: Joe Hershberger

net: phy: dp83867: switch to use phy_get_ofnode()

2018-07-26T19:08:22+00:00

Use PHY API phy_get_ofnode() helper to get PHY DT node.

Signed-off-by: Grygorii Strashko 
Acked-by: Joe Hershberger 
Tested-by: Siva Durga Prasad Paladugu

net: phy: add ofnode node to struct phy_device

2018-07-26T19:08:22+00:00

Now the UCLASS_ETH device "node" field is owerwritten by some network drivers in
case of Ethernet PHYs which are linked to UCLASS_ETH device using
"phy-handle" DT property and when Ethernet PHY driver needs to read some
additional information from DT. In such cases following happens (in
general):

- network drivers
	priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
				   priv->interface);
	<-- phydev is connected to dev which is UCLASS_ETH device

	if (priv->phy_of_handle > 0)
		dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
	<-- phydev->dev->node is overwritten by phy-handle DT node

- PHY driver in .config() callback
	int node = dev_of_offset(dev);
	<-- PHY driver uses overwritten dev->node
        const void *fdt = gd->fdt_blob;

	 if (fdtdec_get_bool(fdt, node, "property"))
		...

As result, UCLASS_ETH device can't be used any more for DT accessing.

This patch adds additional ofnode node field to struct phy_device which can
be set explicitly by network drivers and used by PHY drivers, so
overwriting can be avoided. Also add helper function phy_get_ofnode()
which will check and return phy_device->node or dev_ofnode(phydev->dev) for
backward compatibility with existing drivers.

Signed-off-by: Grygorii Strashko 
Acked-by: Joe Hershberger

net: phy: Clean up includes of common.h

2018-07-26T19:08:22+00:00

We want to be able to include some other system headers in phy.h but
that requires us to have included common.h in the top-level first.

Also, common.h includes config.h as the first thing it does, so don't
include it directly.

Series-to: u-boot
Series-cc: Grygorii Strashko 
Seried-cc: ti
Series-process-log: sort, uniq
Cover-letter:
Prepare for net: phy: prevent uclass_eth device "node" field overwriting
Prepare for [1] so that it doesn't break the build for a bunch of
boards. There are a number of reasons this series broke the build
but none of them depend on changes in the series, so fix up those
situations ahead of applying that series.

[1] https://patchwork.ozlabs.org/cover/940104/
END
Signed-off-by: Joe Hershberger

net: phy: dp83867: switch to use ofnode api

2018-07-26T19:08:21+00:00

Switch to use more generic ofnode API instead of FDT API.

Signed-off-by: Grygorii Strashko 
Acked-by: Joe Hershberger 
Tested-by: Siva Durga Prasad Paladugu

net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap

2018-07-26T19:08:21+00:00

The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017,
advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not
supported (see note below Table 5 (4-Level Strap Pins)).

It further advises that if a board has this pin strapped in mode 1 and
mode 2, then bit[7] of Configuration Register 4 (address 0x0031) must
be cleared to 0. This is to ensure proper operation of PHY.

Since it is not possible to detect in software if RX_DV/RX_CTRL pin is
incorrectly strapped, add a device-tree property to advertise this and
allow corrective action in software.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf

Signed-off-by: Murali Karicheri 
Reviewed-by: Hannes Schmelzer 
Acked-by: Joe Hershberger 
Tested-by: Siva Durga Prasad Paladugu