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<title>u-boot.git/drivers/net, branch v2019.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net?h=v2019.01-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/net?h=v2019.01-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-12-10T22:19:59Z</updated>
<entry>
<title>Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2018-12-10T22:19:59Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-12-10T22:12:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d94604d558cda9f89722c967d6f8d6269a2db21c'/>
<id>urn:sha1:d94604d558cda9f89722c967d6f8d6269a2db21c</id>
<content type='text'>
Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>lib: merge CRC16-CCITT into u-boot/crc.h</title>
<updated>2018-12-09T01:18:32Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2018-11-25T18:22:18Z</published>
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<id>urn:sha1:a740ee913ec8ba04cc53100440f94841648324e2</id>
<content type='text'>
This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure.  Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>armv8: lx2160a: Add LX2160A SoC Support</title>
<updated>2018-12-06T22:37:19Z</updated>
<author>
<name>Priyanka Jain</name>
<email>priyanka.jain@nxp.com</email>
</author>
<published>2018-10-29T09:17:09Z</published>
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<id>urn:sha1:4909b89ec763f0c7030fa8474f9b6c5df866b01f</id>
<content type='text'>
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei &lt;xiaowei.bao@nxp.com&gt;
Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Signed-off-by: Meenakshi Aggarwal &lt;meenakshi.aggarwal@nxp.com&gt;
Signed-off-by: Vabhav Sharma &lt;vabhav.sharma@nxp.com&gt;
Signed-off-by: Sriram Dash &lt;sriram.dash@nxp.com&gt;
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>net: fm: add TFABOOT support</title>
<updated>2018-12-06T22:37:42Z</updated>
<author>
<name>Rajesh Bhagat</name>
<email>rajesh.bhagat@nxp.com</email>
</author>
<published>2018-11-05T18:02:23Z</published>
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<id>urn:sha1:382c53f94631027782ead8147847906b1dcc5d11</id>
<content type='text'>
Adds TFABOOT support and allows to pick FMAN firmware
on basis of boot source.

Signed-off-by: Pankit Garg &lt;pankit.garg@nxp.com&gt;
Signed-off-by: Rajesh Bhagat &lt;rajesh.bhagat@nxp.com&gt;
[YS: fix checkpatch issues]
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'dm-pull-5dec18' of git://git.denx.de/u-boot-dm</title>
<updated>2018-12-06T01:32:25Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-12-06T01:32:25Z</published>
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<id>urn:sha1:2a055ea53260ac8addeeb94eb671172844bc9106</id>
<content type='text'>
Minor sandbox enhancements  / fixes
tpm improvements to clear up v1/v2 support
buildman toolchain fixes
New serial options to set/get config
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-spi</title>
<updated>2018-12-05T20:06:24Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-12-05T20:06:24Z</published>
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<id>urn:sha1:9450ab2ba8d720bd9f73bccc0af2e2b5a2c2aaf1</id>
<content type='text'>
- Various MTD fixes from Boris
- Zap various unused / legacy paths.
- pxa3xx NAND update from Miquel

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>sandbox: net: Correct name copy in eth_raw_bus_post_bind()</title>
<updated>2018-12-05T13:01:34Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2018-11-24T04:29:27Z</published>
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<id>urn:sha1:e628bba785a310e80193f9a34c0b53fcb2136c46</id>
<content type='text'>
We cannot be sure that the interface name takes up the full length of the
space available to it. Use strcpy() instead of memcpy() in this case. This
corrects a valgrind warning.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblaze</title>
<updated>2018-12-04T00:30:54Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-12-04T00:30:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0a3d59e01038a3a50484b8bfcf834376a7215af0'/>
<id>urn:sha1:0a3d59e01038a3a50484b8bfcf834376a7215af0</id>
<content type='text'>
Xilinx changes for v2019.01

microblaze:
- Use default functions for memory decoding
- Showing model from DT

zynq:
- Fix spi flash DTs
- Fix zynq_help_text with CONFIG_SYS_LONGHELP
- Tune cse/mini configurations
- Enabling cse/mini testing with current targets

zynqmp:
- Enable gzip SPL support
- Fix chip detection logic
- Tune mini configurations
- DT fixes(spi-flash, models, clocks, etc)
- Add support for OF_SEPARATE configurations
- Enabling mini testing with current targets
- Add mini mtest configuration
- Some minor config setting

nand:
- arasan: Add subpage configuration

net:
- gem: Add 64bit DMA support
</content>
</entry>
<entry>
<title>net: zynq_gem: Add check for 64-bit dma support by hardware</title>
<updated>2018-12-03T15:22:06Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2018-11-26T10:57:39Z</published>
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<id>urn:sha1:5f68f44c14ab93ffc44a9285e0970cba467276c6</id>
<content type='text'>
This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
<entry>
<title>net: zynq_gem: Added 64-bit addressing support</title>
<updated>2018-12-03T15:22:01Z</updated>
<author>
<name>Vipul Kumar</name>
<email>vipul.kumar@xilinx.com</email>
</author>
<published>2018-11-26T10:57:38Z</published>
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<id>urn:sha1:9a7799f4f4426e690d8c5ab69e6ac34e51029036</id>
<content type='text'>
This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.

Signed-off-by: Vipul Kumar &lt;vipul.kumar@xilinx.com&gt;
Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;monstr@monstr.eu&gt;
</content>
</entry>
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