u-boot.git/drivers/net, branch v2019.04

net: dm: fec: Support phy-reset-post-delay property

2019-04-08T13:23:28+00:00

As per Linux kernel DT binding doc:
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
  a delay of phy-reset-post-delay milliseconds will be observed after the
  phy-reset-gpios has been toggled. Can be omitted thus no delay is
  observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.

Signed-off-by: Andrejs Cainikovs 
Reviewed-by: Anatolij Gustschin 
Reviewed-by: Stefano Babic 
Acked-by: Joe Hershberger 
Acked-by: Lukasz Majewski

net: phy: implement fallback mechanism for negative phy adresses

2019-04-08T00:31:16+00:00

Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.

Signed-off-by: Hannes Schmelzer 
Tested-by: Michal Simek 
Tested-by: Lukasz Majewski

drivers: net: ls1088ardb: Fix EC1 and EC2 RCW offset

2019-03-15T06:22:01+00:00

Fix EC1 and EC2 read from correct offset 26, instead of 25

Signed-off-by: Pramod Kumar 
Acked-by: Joe Hershberger 
Reviewed-by: Prabhakar Kushwaha

mc : Reduce MC memory size to 128M

2019-03-15T06:22:00+00:00

ls2088, ls1088 : minimum MC Memory size is 128 MB
lx2 : minimum MC memory size is 256 MB

Signed-off-by: Meenakshi Aggarwal 
Acked-by: Joe Hershberger 
Reviewed-by: Prabhakar Kushwaha

driver: net: fsl-mc: Fix DPC MAC address fixup

2019-03-15T06:22:00+00:00

If node /board_info/ports does not exist in the DPC file,
function mc_fixup_dpc() will skip not only MAC address fixup,
but also the cache flush at the end. This may cause the other
fixup changes (e.g. ICID related ones) to be ignored by MC.

Fixes: 1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL")

Signed-off-by: Ioana Radulescu 
Acked-by: Joe Hershberger 
Reviewed-by: Prabhakar Kushwaha

drivers: net: ldpaa_eth: check if the dpmac is enabled

2019-03-15T06:22:00+00:00

some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.

Therefore, in fsl_rgmii_init function of SOC, we will check if the
dpmac is enabled or not? if it is (fsl_serdes_init has already enabled
the dpmac), then don't enable it.

Signed-off-by: Pankaj Bansal 
Acked-by: Joe Hershberger 
Reviewed-by: Prabhakar Kushwaha

drivers/net/fec: phy_init: remove redundant logic

2019-03-13T08:14:35+00:00

The phy_connect_dev(...) function from phy.c does all the handling
(inclusive catching fixed-link).

So we drop here the single steps and call just phy_connect_dev(...).

Signed-off-by: Hannes Schmelzer 
Acked-by: Joe Hershberger

net: macb: Fix GEM hardware detection

2019-02-27T01:12:33+00:00

Fix MID bit field check to correctly identify all GEM hardwares.

The check is updated as per macb driver in Linux location:
/drivers/net/ethernet/cadence/macb_main.c:259

Signed-off-by: Atish Patra 
Signed-off-by: Anup Patel 
Reviewed-by: Alexander Graf 
Reviewed-by: Lukas Auer 
Acked-by: Joe Hershberger

net: macb: Fix clk API usage for RISC-V systems

2019-02-27T01:12:33+00:00

Don't fail in macb_enable_clk() if clk_enable() returns
-ENOSYS because we get -ENOSYS for fixed-rate clocks.

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng

arm: socfpga: gen5 enable designware_socfpga

2019-02-18T12:00:53+00:00

Enable the socfpga specific designware ethernet driver by default for
socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a
MACH_SOCFPGA config.

This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt