u-boot.git/drivers/net, branch v2019.04-rc4

drivers: net: ls1088ardb: Fix EC1 and EC2 RCW offset

2019-03-15T06:22:01Z

Fix EC1 and EC2 read from correct offset 26, instead of 25 Signed-off-by: Pramod Kumar Acked-by: Joe Hershberger Reviewed-by: Prabhakar Kushwaha

mc : Reduce MC memory size to 128M

2019-03-15T06:22:00Z

ls2088, ls1088 : minimum MC Memory size is 128 MB lx2 : minimum MC memory size is 256 MB Signed-off-by: Meenakshi Aggarwal Acked-by: Joe Hershberger Reviewed-by: Prabhakar Kushwaha

driver: net: fsl-mc: Fix DPC MAC address fixup

2019-03-15T06:22:00Z

If node /board_info/ports does not exist in the DPC file, function mc_fixup_dpc() will skip not only MAC address fixup, but also the cache flush at the end. This may cause the other fixup changes (e.g. ICID related ones) to be ignored by MC. Fixes: 1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL") Signed-off-by: Ioana Radulescu Acked-by: Joe Hershberger Reviewed-by: Prabhakar Kushwaha

drivers: net: ldpaa_eth: check if the dpmac is enabled

2019-03-15T06:22:00Z

some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal Acked-by: Joe Hershberger Reviewed-by: Prabhakar Kushwaha

drivers/net/fec: phy_init: remove redundant logic

2019-03-13T08:14:35Z

The phy_connect_dev(...) function from phy.c does all the handling (inclusive catching fixed-link). So we drop here the single steps and call just phy_connect_dev(...). Signed-off-by: Hannes Schmelzer Acked-by: Joe Hershberger

net: macb: Fix GEM hardware detection

2019-02-27T01:12:33Z

Fix MID bit field check to correctly identify all GEM hardwares. The check is updated as per macb driver in Linux location: /drivers/net/ethernet/cadence/macb_main.c:259 Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Alexander Graf Reviewed-by: Lukas Auer Acked-by: Joe Hershberger

net: macb: Fix clk API usage for RISC-V systems

2019-02-27T01:12:33Z

Don't fail in macb_enable_clk() if clk_enable() returns -ENOSYS because we get -ENOSYS for fixed-rate clocks. Signed-off-by: Anup Patel Reviewed-by: Bin Meng

arm: socfpga: gen5 enable designware_socfpga

2019-02-18T12:00:53Z

Enable the socfpga specific designware ethernet driver by default for socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a MACH_SOCFPGA config. This is required to remove the hacky reset and phy mode handling in arch/arm/mach-socfpga. Signed-off-by: Simon Goldschmidt

net: designware: socfpga: adapt to Gen5

2019-02-18T12:00:53Z

This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is probably why it has been ignored. By using this offset when writing the phy mode into the syscon regiter, we can use this driver to set the phy mode for both of the MACs on Gen5. Since the PHY mode bits in sysmgr are the same even for Stratix10, let's drop the detection of the sub-mach by checking compatible version and just use the same code for all FPGAs. To work correctly, this driver depends on SYSCON and REGMAP, so select those via Kconfig when it is enabeld. Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift offset is required). Signed-off-by: Simon Goldschmidt

net: mv88e61xx: fix autonegotiation on ports

2019-02-15T12:01:28Z

phy_reset should be called before autoneg is setup The only boards using MV88E61XX_SWITCH are: - alliedtelesis/SBx81LIFKW - alliedtelesis/SBx81LIFXCAT - gateworks/gw_ventana Cc: Chris Packham Signed-off-by: Tim Harvey Reviewed-by: Chris Packham