u-boot.git/drivers/net, branch v2020.04

net: sh_eth: Init the hardware before PHY access

2020-04-04T13:06:37+00:00

To access the PHY, the MAC registers must be initialized. Call the init
function in probe() to make it so, otherwise the PHY ID readout returns
all zeroes.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Nobuhiro Iwamatsu

net: macb: Fix incorrect write function name when MACB_ZYNQ is enabled.

2020-03-31T14:06:53+00:00

When MACB_ZYNQ is enabled there is compilation warnings
drivers/net/macb.c: In function ‘_macb_init’:
drivers/net/macb.h:675:33: error: ‘MACB_DMACFG’ undeclared (first use in this function);
 did you mean ‘MACB_MCF’?
  writel((value), (port)->regs + MACB_##reg)
                                 ^~~~~

It has been caused by changing macros name by commit below.

Fixes: 6c636514d499 ("net: macb: sync header definitions as taken from Linux")
Signed-off-by: Michal Simek 
Acked-by: Joe Hershberger

armv8/ls1046ardb: RGMII ports require internal delay

2020-03-30T02:36:52+00:00

The correct setting for the RGMII ports on LS1046ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.

Fixes: cc1aa218f510 ("armv8/ls1046a: RGMII PHY requires internal
	delay on Tx")
Signed-off-by: Madalin Bucur 
Reviewed-by: Priyanka Jain

armv8/ls1043ardb: RGMII ports require internal delay

2020-03-30T02:36:52+00:00

The correct setting for the RGMII ports on LS1043ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID. There is a pull-up that turns
on Rx internal delay by default and the u-boot does not
override that (yet) so in u-boot the interface is functional.
In Linux the PHY driver is clearing the Rx delay for the
"rgmii-txid" mode and the reception does not work.
Changing the RGMII mode to internal delay here ensures that
device tree fix-ups for the PHY connection type turn on both
Tx and Rx internal delay in Linux.

Fixes: 5a78a472f666 ("armv8/ls1043a: RGMII PHY requires internal
	delay on Tx")
Signed-off-by: Madalin Bucur 
Reviewed-by: Priyanka Jain

net: fman: add support for all RGMII delay modes

2020-03-30T02:36:52+00:00

The RGMII modes that include internal delay were not all
properly treated in the memac code. Add support for all
RGMII delay modes.

Fixes: 111fd19e3b9e ("fm/mEMAC: add mEMAC frame work")
Signed-off-by: Madalin Bucur 
Reviewed-by: Priyanka Jain

net: phy: marvell: Unify 88E151x series phy_driver

2020-03-09T23:11:25+00:00

The PHY models of the Marvell 88E151x series are not reliably
distinguishable by their uid / PHY identifiers.
The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and
model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are
described as HW revision number, but both 88E1510 and 88E1518 PHYs were
observed with the same HW rev number (1).

Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify
Marvell 88E1518"), the 88E151x were detected because the HW revision
bits were masked from the uid. After that change, 88E1510/12/18 were all
detected as 88E1518 and the 88E1510 specific code was no longer run.

I modified the mask to again ignore all four HW revision bits, removed
the 88E1510 specific code (board-specific LED/INTn setup), which was not
called since late 2016 anyway and renamed the config function and
phy_driver struct to the better fitting 88e151x.

The uid and mask bits 3:0 are now again the same as in the Linux kernel.

Signed-off-by: Clemens Gruber

net: phy: dp83867: Add SGMII mode type switching

2020-03-09T23:11:25+00:00

This patch adds ability to switch beetween two PHY SGMII modes.
Some hardware, for example, FPGA IP designs may use 6-wire mode
which enables differential SGMII clock to MAC.

Patch description, dt flags have been done in mainline Linux by
commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type")
and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")

Signed-off-by: Michal Simek 
Acked-by: Joe Hershberger

net: phy: Fix overlong PHY timeout

2020-03-09T23:11:24+00:00

Commit 27c3f70f3b50 ("net: phy: Increase link up delay in
genphy_update_link()") increased the per-iteration waiting time from
1ms to 50ms, without adjusting the timeout counter. This lead to the
timeout increasing from the typical 4 seconds to over three minutes.

Adjust the timeout counter evaluation by that factor of 50 to bring the
timeout back to the intended value.

Signed-off-by: Andre Przywara 
Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50")
Reviewed-by: Stefan Roese 
Tested-by: Matthias Brugger 
Tested-by: Simon Goldschmidt 
Acked-by: Joe Hershberger

drivers: net: phy: aquantia: make it less verbose

2020-03-09T23:11:24+00:00

The driver now unconditionally prints some information that's not
universally useful.  Replace printf with debug.

Signed-off-by: Alex Marginean 
Reviewed-by: Priyanka Jain 
Acked-by: Joe Hershberger

drivers: net: phy: aquantia: drop XGMII as a valid system interface proto

2020-03-09T23:11:24+00:00

Use either USXGMII or XFI in aquantia_set_proto and drop XGMII as a valid
protocol configuration.  The PHY doesn't support it, it's just used as an
alias for one of the other two protocols.

Signed-off-by: Florin Chiculita 
Signed-off-by: Alex Marginean 
Reviewed-by: Priyanka Jain 
Acked-by: Joe Hershberger