u-boot.git/drivers/net, branch v2020.07

net: fec: Allow the PHY node to be retrieved

2020-06-22T15:40:49+00:00

As we move towards driver model, it is required to let the FEC driver
know how to properly deal with an Ethernet PHY subnode in the device tree.

For example:

 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
	phy-handle = <&phy>;
 	phy-mode = "rgmii-id";
 	phy-reset-duration = <2>;
 	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		phy: ethernet-phy@0 {
			reg = <0>;
			qca,clk-out-frequency = <125000000>;
		};
	};
 };

Currently the PHY node pointer is incorrectly associated with the
Ethernel controller instead of the PHY node itself.

This causes the PHY properties, such as "qca,clk-out-frequency" in
the example above to not get parsed.

Fix this problem by populating the phy_of_node node.

Suggested-by: Vladimir Oltean 
Signed-off-by: Fabio Estevam 
Tested-by: Tom Rini

phy: atheros: ar8035: Fix clock output calculation

2020-06-22T15:40:41+00:00

The clock ouput frequency is calculated incorrectly for AR8035 due to
wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.

This same issue has been already fixed in the kernel by:

commit b1f4c209d84057b6d40b939b6e4404854271d797
Author: Oleksij Rempel 
Date:   Wed Apr 1 11:57:32 2020 +0200

    net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035

    The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
    for the values that comprise the fields, not zero-bits-set.

    This patch fixes the clock frequency configuration for ATH8030 and
    ATH8035 Atheros PHYs by removing the erroneous "~".

    To reproduce this bug, configure the PHY  with the device tree binding
    "qca,clk-out-frequency" and remove the machine specific PHY fixups.

    Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
    Signed-off-by: Oleksij Rempel 
    Reported-by: Russell King 
    Reviewed-by: Russell King 
    Tested-by: Russell King 
    Signed-off-by: David S. Miller 

Apply the same fix in the U-Boot driver.

Tested on a i.MX6 Hummingboard.

Signed-off-by: Fabio Estevam 
Reviewed-by: Michael Walle 
Tested-by: Tom Rini

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

2020-06-08T12:51:59+00:00

- DM_ETH support for P2041RDB, T1024RDB, P5040DS, P3041DS, P4080DS, bug
  fixes
- Add TBI PHY access through MII
- DDR: Rework errata workaround for A008109, A008378, 009942

net: tsec: Access TBI PHY through the corresponding MII

2020-06-04T13:23:20+00:00

When an eTSEC is configured to use TBI, configuration of the
TBI is done through the MIIM registers for that eTSEC.
For example, if a TBI interface is required on eTSEC2, then
the MIIM registers starting at offset 0x2_5520 are used to
configure it.

Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support")
Signed-off-by: Hou Zhiqiang 
Reviewed-by: Vladimir Oltean 
Tested-by: Vladimir Oltean 
Reviewed-by: Priyanka Jain

net: tsec: Access eTSEC registers using virtual address

2020-06-04T13:23:20+00:00

The current code accesses eTSEC registers using physical
address directly, it's not correct, though no problem on
current platforms. It won't work on platforms, which does
not support 1:1 virtual-physical address map.

Signed-off-by: Hou Zhiqiang 
Reviewed-by: Vladimir Oltean 
Tested-by: Vladimir Oltean 
Reviewed-by: Priyanka Jain

net: tsec: fsl_mdio: add DM MDIO support

2020-06-04T13:23:14+00:00

Allow the MDIO devices to be probed based on the device tree.

Signed-off-by: Madalin Bucur 
Signed-off-by: Priyanka Jain

drivers: net: e1000: with DM_ETH needs DM_PCI too

2020-06-03T06:44:27+00:00

Compilation error occur when DM_ETH is enabled without DM_PCI.

Signed-off-by: Madalin Bucur 
Reviewed-by: Priyanka Jain

net: sun8i_emac: Add support for the H6 variant

2020-06-01T17:08:37+00:00

The H6 EMAC is very similar to the H3 variant, except that it uses the
same pinmux as R40. Add support for it.

Signed-off-by: Samuel Holland 
Reviewed-by: Jagan Teki

net: sun8i_emac: Use consistent clock bitfield definitions

2020-06-01T17:08:22+00:00

While the R40 uses a different register for EMAC clock configuration
than other chips, the register has a very similar layout. Reuse the
existing bitfield definitions in this file, since they match.

This allows the driver to compile on the H6 platform, where the
CCM_GMAC_CTRL definitions are not present.

Signed-off-by: Samuel Holland 
Reviewed-by: Jagan Teki

net: ks8851: Add Kconfig entries

2020-05-22T17:46:45+00:00

Convert CONFIG_KS8851_MLL and CONFIG_KS8851_MLL_BASEADDR to Kconfig

Signed-off-by: Marek Vasut 
Cc: Eugen Hristev 
Cc: Joe Hershberger