u-boot.git/drivers/net, branch v2021.01-rc2

net: ks8851: Implement EEPROM MAC address readout

2020-11-09T19:18:09Z

In case there is an EEPROM attached to the KS8851 MAC and the EEPROM contains a valid MAC address, the MAC address is loaded into the NIC registers on power on. Read the MAC address out of the NIC registers and provide it to U-Boot. Signed-off-by: Marek Vasut Cc: Eugen Hristev Cc: Joe Hershberger

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

2020-10-29T13:10:24Z

- Bug fixes and updates on vid, ls1088a lx2160a and other layerscape platforms. - Add optee_rpmb support for LX2 & Kontron sl28 support

net: lx2160a.c: Update to set ECx_PMUX precedence

2020-10-23T11:22:09Z

As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan [Rebased] Signed-off-by: Priyanka Jain

Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi

2020-10-23T00:32:02Z

- sun8i emac changes (Andre) - SCP firmware (Samuel)

net: Add IPQ40xx MDIO driver

2020-10-22T13:54:54Z

This adds the driver for the IPQ40xx built-in MDIO. This will be needed to support future PHY driver. Signed-off-by: Robert Marko Cc: Luka Perkov

net: sun8i-emac: Lower MDIO frequency

2020-10-21T18:15:39Z

When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Tested-by: Amit Singh Tomar # Pine64+ Reviewed-by: Jagan Teki

net: sun8i-emac: Make internal PHY handling more robust

2020-10-21T18:15:23Z

The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara [jagan: rebase on master] Signed-off-by: Jagan Teki Acked-by: Maxime Ripard Tested-by: Amit Singh Tomar # Pine64+ Reviewed-by: Jagan Teki

net: sun8i_emac: Simplify and fix error handling for RX

2020-10-21T18:15:06Z

The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Tested-by: Amit Singh Tomar # Pine64+ Reviewed-by: Jagan Teki

net: sun8i_emac: Fix MAC soft reset

2020-10-21T18:14:52Z

The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Tested-by: Amit Singh Tomar # Pine64+ Reviewed-by: Jagan Teki

net: sun8i_emac: Fix overlong lines

2020-10-21T18:14:40Z

When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard Tested-by: Amit Singh Tomar # Pine64+ Reviewed-by: Jagan Teki