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<title>u-boot.git/drivers/net, branch v2021.07-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net?h=v2021.07-rc3</id>
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<updated>2021-05-20T11:03:35Z</updated>
<entry>
<title>net: mvpp2: add explicit sgmii-2500 support</title>
<updated>2021-05-20T11:03:35Z</updated>
<author>
<name>Marcin Wojtas</name>
<email>mw@semihalf.com</email>
</author>
<published>2021-05-03T06:08:53Z</published>
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<id>urn:sha1:d24efc621c4953eaca3c59da0a9c228354044912</id>
<content type='text'>
Until now the mvpp2 driver used an extra 'phy-speed'
DT property in order to differentiate between the
SGMII and SGMII @2.5GHz. As there is a dedicated
PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter
start using it and drop the custom flag.

Signed-off-by: Marcin Wojtas &lt;mw@semihalf.com&gt;
Reviewed-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Reviewed-by: Nadav Haklai &lt;nadavh@marvell.com&gt;
Tested-by: Nadav Haklai &lt;nadavh@marvell.com&gt;

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Ramon Fried &lt;rfried.dev@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: mvpp2: allow MDIO registration for fixed links</title>
<updated>2021-05-20T11:03:31Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2021-05-03T06:08:52Z</published>
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<id>urn:sha1:27844000ef5f6717570789cace60af76f739f564</id>
<content type='text'>
Currently, there are 2 valid cases for interface, PHY
and mdio relation:
  - If an interface has PHY handler, it'll call
    mdio_mii_bus_get_from_phy(), which will register
    MDIO bus.
  - If we want to use fixed-link for an interface,
    PHY handle is not defined in the DTS, and no
    MDIO is registered.

There is a third case, for some boards (with switch),
the MDIO is used for switch configuration, but the interface
itself uses fixed link. This patch allows this option by
checking if fixed-link subnode is defined, in this case,
MDIO bus is registers, but the PHY address is set to
PHY_MAX_ADDR for this interface, so this interface will
not try to access the PHY later on.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2: fix missing switch case break</title>
<updated>2021-05-20T11:03:30Z</updated>
<author>
<name>Ben Peled</name>
<email>bpeled@marvell.com</email>
</author>
<published>2021-05-03T06:08:51Z</published>
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<id>urn:sha1:d757c859c758330bccf460d6c192109fc94b1443</id>
<content type='text'>
Signed-off-by: Ben Peled &lt;bpeled@marvell.com&gt;
Reviewed-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Reviewed-by: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Ramon Fried &lt;rfried.dev@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REG</title>
<updated>2021-05-20T11:03:30Z</updated>
<author>
<name>Ben Peled</name>
<email>bpeled@marvell.com</email>
</author>
<published>2021-05-03T06:08:50Z</published>
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<id>urn:sha1:cf51a0d5fce0f040748365aa6f3eb9a5b70884ea</id>
<content type='text'>
Signed-off-by: Ben Peled &lt;bpeled@marvell.com&gt;
Reviewed-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Reviewed-by: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Ramon Fried &lt;rfried.dev@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: mvpp2: AN Bypass in 1000 and 2500 basex mode</title>
<updated>2021-05-20T11:03:30Z</updated>
<author>
<name>Ben Peled</name>
<email>bpeled@marvell.com</email>
</author>
<published>2021-05-03T06:08:49Z</published>
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<id>urn:sha1:7589be8d3841062d933aa851186a7d3cb60f97b7</id>
<content type='text'>
Signed-off-by: Ben Peled &lt;bpeled@marvell.com&gt;
Reviewed-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Reviewed-by: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2: Fix 2.5G GMII_SPEED configurations</title>
<updated>2021-05-20T11:03:30Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2021-05-03T06:08:48Z</published>
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<id>urn:sha1:08f462dd1eb86a81493e12e2bbb974158cee52b3</id>
<content type='text'>
GMII_SPEED should be enabled for 2.5G speed

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Reviewed-by: Yan Markman &lt;ymarkman@marvell.com&gt;
Reviewed-by: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: mvpp2: remove redundant SMI address configuration</title>
<updated>2021-05-20T11:03:30Z</updated>
<author>
<name>Marcin Wojtas</name>
<email>mw@semihalf.com</email>
</author>
<published>2021-05-03T06:08:47Z</published>
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<id>urn:sha1:be45eb5064190c79e916cd702910318194f9c8a2</id>
<content type='text'>
Because the mvpp2 driver now relies on the PHYLIB and
the external MDIO driver, configuring low level
SMI bus settings is redundant.

Signed-off-by: Marcin Wojtas &lt;mw@semihalf.com&gt;
Reviewed-by: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Reviewed-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Ramon Fried &lt;rfried.dev@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: mvpp2: add 1000BaseX and 2500BaseX ppv2 support</title>
<updated>2021-05-20T11:03:30Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2021-05-03T06:08:46Z</published>
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<id>urn:sha1:8299abc5ff0b5c2403a3f085376247d4cd8c37d1</id>
<content type='text'>
Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Ramon Fried &lt;rfried.dev@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: mvpp2: add CP115 port1 10G/5G SFI support</title>
<updated>2021-05-20T11:03:30Z</updated>
<author>
<name>Stefan Chulski</name>
<email>stefanc@marvell.com</email>
</author>
<published>2021-05-03T06:08:45Z</published>
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<id>urn:sha1:8d3aa376a9e4b410adf4d45cf529c0c2e748165f</id>
<content type='text'>
1. Differ between Port1 RGMII and SFI modes in Netcomplex config.
2. Remove XPCS config from SFI mode.
   Port1 doesn't XPCS domain, XPCS config should be removed.
   Access to Port1 XPCS can cause stall.
3. Add Port1 MPCS configurations.

Signed-off-by: Stefan Chulski &lt;stefanc@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>net: designware: meson8b: add g12a compatible</title>
<updated>2021-05-14T15:46:50Z</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2021-04-16T12:52:06Z</published>
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<id>urn:sha1:4c2eb955cfd77d667485c5141cda2821aa1f97ef</id>
<content type='text'>
Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
</entry>
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