u-boot.git/drivers/net, branch v2024.01 Unnamed repository; edit this file 'description' to name the repository. net: sun8i_emac: Drop DM_GPIO checks 2023-11-12T16:45:03+00:00 Samuel Holland samuel@sholland.org 2023-10-31T05:25:46+00:00 7b252df7ca574df34de5a8eb8fff62444c5df5f5 DM_GPIO is always enable in U-Boot proper for ARCH_SUNXI, and this driver is never enabled in SPL, so the condition is always true. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> 
DM_GPIO is always enable in U-Boot proper for ARCH_SUNXI, and this
driver is never enabled in SPL, so the condition is always true.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
tree-wide: Replace http:// link with https:// link for ti.com 2023-11-10T16:01:50+00:00 Nishanth Menon nm@ti.com 2023-11-01T20:56:03+00:00 a94a4071d449e12c9fb5ac37d6362d22efcb27da Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> 
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon <nm@ti.com>
net: designware: add DMA offset awareness 2023-11-05T21:11:38+00:00 Baruch Siach baruch@tkos.co.il 2023-10-25T08:08:44+00:00 d44f3d21fe4420709b5a09379b809a3b92b7fa07 Older DesignWare Ethernet MAC versions that this driver supports can only work with 32-bit DMA source/destination addresses. Some platforms have no physical RAM at the lowest 4GB address space. For these platforms the driver must translate DMA addresses to/from physical memory addresses. Call translation routines so that properly configured platforms can use the DesignWare Ethernet MAC. For platforms using device-tree this usually means adding dma-ranges property to the bus the device node is in. Signed-off-by: Baruch Siach <baruch@tkos.co.il> 
Older DesignWare Ethernet MAC versions that this driver supports can
only work with 32-bit DMA source/destination addresses. Some platforms
have no physical RAM at the lowest 4GB address space. For these
platforms the driver must translate DMA addresses to/from physical
memory addresses.

Call translation routines so that properly configured platforms can use
the DesignWare Ethernet MAC. For platforms using device-tree this
usually means adding dma-ranges property to the bus the device node is
in.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
net: e1000: Drop e1000_eth_ids[] 2023-11-05T21:11:38+00:00 Bin Meng bmeng@tinylab.org 2023-10-11T10:58:25+00:00 9e4cabcf4356d13ad0abb602278b34e4a7ca57ae e1000_eth_ids holds compatible strings for e1000 devices, but it is meaningless as e1000 is a PCI device and there is no such compatible string assigned to e1000 by the DT bindings community. Drop it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> 
e1000_eth_ids holds compatible strings for e1000 devices, but it
is meaningless as e1000 is a PCI device and there is no such
compatible string assigned to e1000 by the DT bindings community.

Drop it.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
net: phy: TI DP83869 fix invalid clock delay configuration 2023-11-05T21:11:38+00:00 Frank de Brabander debrabander@gmail.com 2023-10-06T12:24:39+00:00 a56e30e65f2549fd8dff32ecfe24992178414f09 Setting the clock delay from the device tree settings rx-internal-delay-ps and tx-internal-delay-ps was broken: - The expected value in the device tree is suppose to be a delay in picoseconds, but the driver only allowed an array index. - Driver converted this array index to the actual delay in picoseconds and tried to apply this in the device register. This however is not a valid register value. The actual logic here was reversed, it converted an register representation of the delay to the device tree delay in picoseconds. Only when the internal delays were NOT configured in the device tree and they default value of 7 (=2000ps) was used, a valid value was loaded in the register. Signed-off-by: Frank de Brabander <debrabander@gmail.com> 
Setting the clock delay from the device tree settings
rx-internal-delay-ps and tx-internal-delay-ps was broken:

 - The expected value in the device tree is suppose to be a
   delay in picoseconds, but the driver only allowed an array index.
 - Driver converted this array index to the actual delay in
   picoseconds and tried to apply this in the device register. This
   however is not a valid register value. The actual logic here was
   reversed, it converted an register representation of the delay to
   the device tree delay in picoseconds.

Only when the internal delays were NOT configured in the device tree
and they default value of 7 (=2000ps) was used, a valid value was
loaded in the register.

Signed-off-by: Frank de Brabander <debrabander@gmail.com>
net: add hifemac_mdio MDIO bus driver for HiSilicon platform 2023-11-05T21:11:38+00:00 Yang Xiwen forbidden405@outlook.com 2023-08-22T17:03:43+00:00 6b5c8d98e2043d321216961ba67edb757a1a16eb It adds the driver for the internal MDIO bus of HIFEMAC Ethernet controller. It's based on the mainstream linux driver. Signed-off-by: Yang Xiwen <forbidden405@outlook.com> 
It adds the driver for the internal MDIO bus of HIFEMAC Ethernet
controller.  It's based on the mainstream linux driver.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
net: add hifemac Ethernet driver for HiSilicon platform 2023-11-05T21:11:38+00:00 Yang Xiwen forbidden405@outlook.com 2023-08-22T17:03:42+00:00 9d8f78a2a79f7e40606da129fa85f8edad15b4a1 It adds the driver for HIFEMAC Ethernet controller found on HiSilicon SoCs like Hi3798MV200. It's based on the mainstream linux driver, but quite a lot of code gets rewritten and cleaned up to adopt u-boot driver model. Signed-off-by: Yang Xiwen <forbidden405@outlook.com> 
It adds the driver for HIFEMAC Ethernet controller found on HiSilicon
SoCs like Hi3798MV200.  It's based on the mainstream linux driver, but
quite a lot of code gets rewritten and cleaned up to adopt u-boot driver
model.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
net: mv88e6xxx: add Clause 45 support 2023-11-05T21:11:37+00:00 Robert Marko robert.marko@sartura.hr 2023-08-08T16:05:16+00:00 89943052e465a1883441d4a58f8e9528eaeaf744 Marvell LinkStreet switches support Clause 45 MDIO on the internal bus. C45 read or writes require the register address to be written first to the SMI PHY Data register, and then a special C45 Write Address Register OP is used on the SMI PHY Register before making a C45 Read Data Register OP and being able to actually read the register. Signed-off-by: Robert Marko <robert.marko@sartura.hr> 
Marvell LinkStreet switches support Clause 45 MDIO on the internal bus.

C45 read or writes require the register address to be written first to
the SMI PHY Data register, and then a special C45 Write Address Register
OP is used on the SMI PHY Register before making a C45 Read Data Register
OP and being able to actually read the register.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
net: mv88e6xxx: use generic bitfield macros for MDIO 2023-11-05T18:28:40+00:00 Robert Marko robert.marko@sartura.hr 2023-08-08T16:05:15+00:00 1aecba9c1b77e83fe589797d12d4dbbd14a8a3c8 Driver is currently defining the mask and bit shifting itself, there is no need for that as U-Boot has generic bitfield macros that help us achieve the same result but in a cleaner way. Signed-off-by: Robert Marko <robert.marko@sartura.hr> 
Driver is currently defining the mask and bit shifting itself,
there is no need for that as U-Boot has generic bitfield macros that help
us achieve the same result but in a cleaner way.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
net: ftgmac100: Add reset control 2023-11-05T18:28:40+00:00 Dylan Hung kobedylan@gmail.com 2023-07-27T01:58:14+00:00 607e7fa622b155865612bd668e3b39f7f2a1069e Add optional reset control, especially for the Aspeed SOC. For the hardware without a reset line, the reset assertion/deassertion will be skipped. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> 
Add optional reset control, especially for the Aspeed SOC. For the
hardware without a reset line, the reset assertion/deassertion will be
skipped.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>