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<title>u-boot.git/drivers/net, branch v2024.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/net?h=v2024.01-rc2</id>
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<updated>2023-11-05T21:11:38Z</updated>
<entry>
<title>net: designware: add DMA offset awareness</title>
<updated>2023-11-05T21:11:38Z</updated>
<author>
<name>Baruch Siach</name>
<email>baruch@tkos.co.il</email>
</author>
<published>2023-10-25T08:08:44Z</published>
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<id>urn:sha1:d44f3d21fe4420709b5a09379b809a3b92b7fa07</id>
<content type='text'>
Older DesignWare Ethernet MAC versions that this driver supports can
only work with 32-bit DMA source/destination addresses. Some platforms
have no physical RAM at the lowest 4GB address space. For these
platforms the driver must translate DMA addresses to/from physical
memory addresses.

Call translation routines so that properly configured platforms can use
the DesignWare Ethernet MAC. For platforms using device-tree this
usually means adding dma-ranges property to the bus the device node is
in.

Signed-off-by: Baruch Siach &lt;baruch@tkos.co.il&gt;
</content>
</entry>
<entry>
<title>net: e1000: Drop e1000_eth_ids[]</title>
<updated>2023-11-05T21:11:38Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng@tinylab.org</email>
</author>
<published>2023-10-11T10:58:25Z</published>
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<id>urn:sha1:9e4cabcf4356d13ad0abb602278b34e4a7ca57ae</id>
<content type='text'>
e1000_eth_ids holds compatible strings for e1000 devices, but it
is meaningless as e1000 is a PCI device and there is no such
compatible string assigned to e1000 by the DT bindings community.

Drop it.

Signed-off-by: Bin Meng &lt;bmeng@tinylab.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>net: phy: TI DP83869 fix invalid clock delay configuration</title>
<updated>2023-11-05T21:11:38Z</updated>
<author>
<name>Frank de Brabander</name>
<email>debrabander@gmail.com</email>
</author>
<published>2023-10-06T12:24:39Z</published>
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<id>urn:sha1:a56e30e65f2549fd8dff32ecfe24992178414f09</id>
<content type='text'>
Setting the clock delay from the device tree settings
rx-internal-delay-ps and tx-internal-delay-ps was broken:

 - The expected value in the device tree is suppose to be a
   delay in picoseconds, but the driver only allowed an array index.
 - Driver converted this array index to the actual delay in
   picoseconds and tried to apply this in the device register. This
   however is not a valid register value. The actual logic here was
   reversed, it converted an register representation of the delay to
   the device tree delay in picoseconds.

Only when the internal delays were NOT configured in the device tree
and they default value of 7 (=2000ps) was used, a valid value was
loaded in the register.

Signed-off-by: Frank de Brabander &lt;debrabander@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: add hifemac_mdio MDIO bus driver for HiSilicon platform</title>
<updated>2023-11-05T21:11:38Z</updated>
<author>
<name>Yang Xiwen</name>
<email>forbidden405@outlook.com</email>
</author>
<published>2023-08-22T17:03:43Z</published>
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<id>urn:sha1:6b5c8d98e2043d321216961ba67edb757a1a16eb</id>
<content type='text'>
It adds the driver for the internal MDIO bus of HIFEMAC Ethernet
controller.  It's based on the mainstream linux driver.

Signed-off-by: Yang Xiwen &lt;forbidden405@outlook.com&gt;
</content>
</entry>
<entry>
<title>net: add hifemac Ethernet driver for HiSilicon platform</title>
<updated>2023-11-05T21:11:38Z</updated>
<author>
<name>Yang Xiwen</name>
<email>forbidden405@outlook.com</email>
</author>
<published>2023-08-22T17:03:42Z</published>
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<id>urn:sha1:9d8f78a2a79f7e40606da129fa85f8edad15b4a1</id>
<content type='text'>
It adds the driver for HIFEMAC Ethernet controller found on HiSilicon
SoCs like Hi3798MV200.  It's based on the mainstream linux driver, but
quite a lot of code gets rewritten and cleaned up to adopt u-boot driver
model.

Signed-off-by: Yang Xiwen &lt;forbidden405@outlook.com&gt;
</content>
</entry>
<entry>
<title>net: mv88e6xxx: add Clause 45 support</title>
<updated>2023-11-05T21:11:37Z</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2023-08-08T16:05:16Z</published>
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<id>urn:sha1:89943052e465a1883441d4a58f8e9528eaeaf744</id>
<content type='text'>
Marvell LinkStreet switches support Clause 45 MDIO on the internal bus.

C45 read or writes require the register address to be written first to
the SMI PHY Data register, and then a special C45 Write Address Register
OP is used on the SMI PHY Register before making a C45 Read Data Register
OP and being able to actually read the register.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
</content>
</entry>
<entry>
<title>net: mv88e6xxx: use generic bitfield macros for MDIO</title>
<updated>2023-11-05T18:28:40Z</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2023-08-08T16:05:15Z</published>
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<id>urn:sha1:1aecba9c1b77e83fe589797d12d4dbbd14a8a3c8</id>
<content type='text'>
Driver is currently defining the mask and bit shifting itself,
there is no need for that as U-Boot has generic bitfield macros that help
us achieve the same result but in a cleaner way.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
</content>
</entry>
<entry>
<title>net: ftgmac100: Add reset control</title>
<updated>2023-11-05T18:28:40Z</updated>
<author>
<name>Dylan Hung</name>
<email>kobedylan@gmail.com</email>
</author>
<published>2023-07-27T01:58:14Z</published>
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<id>urn:sha1:607e7fa622b155865612bd668e3b39f7f2a1069e</id>
<content type='text'>
Add optional reset control, especially for the Aspeed SOC. For the
hardware without a reset line, the reset assertion/deassertion will be
skipped.

Signed-off-by: Dylan Hung &lt;dylan_hung@aspeedtech.com&gt;
Reviewed-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
Reviewed-by: Ramon Fried &lt;rfried.dev@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: dw_eth_qos: Add 64-bit addressing</title>
<updated>2023-11-05T18:28:40Z</updated>
<author>
<name>Ley Foon Tan</name>
<email>leyfoon.tan@starfivetech.com</email>
</author>
<published>2022-12-09T06:33:14Z</published>
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<id>urn:sha1:5d260d08009e9bf4b4aec0e414e68ab30e784602</id>
<content type='text'>
Set upper 32bit address for DMA descriptors and buffer address to support
64-bit addressing.

Signed-off-by: Ley Foon Tan &lt;leyfoon.tan@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>sunxi: remove CONFIG_MACPWR</title>
<updated>2023-10-22T22:40:56Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-06-08T13:56:56Z</published>
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<id>urn:sha1:5ad98c57b8dc465b7d1534203b75dc2b35440457</id>
<content type='text'>
The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
the power for the Ethernet "MAC" (mostly PHY, really).
In the DT this is described with the phy-supply property in the MAC DT
node, pointing to a (GPIO controlled) regulator. Since we need Ethernet
only in U-Boot proper, and use a DM driver there, we should use the DT
instead of hardcoding this.

Add code to the sun8i_emac and sunxi_emac drivers to check the DT for
that regulator and enable it, at probe time. Then drop the current code
from board.c, which was doing that job before.
This allows us to remove the MACPWR Kconfig definition and the respective
values from the defconfigs.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Sam Edwards &lt;CFSworks@gmail.com&gt;
</content>
</entry>
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