u-boot.git/drivers/net, branch v2025.04-rc2

net: designware: support phy io micro voltage setting.

2025-02-10T16:28:36Z

Support phy io micro voltage setting for NPCM8XX rgmii interface. Signed-off-by: Michael Chang

net: miiphybb: Update debug() print

2025-02-04T22:34:42Z

Update the debug() print, use __func__ to always print matching function name, and also print bus name in case there are multiple busses. Signed-off-by: Marek Vasut Reviewed-by: Paul Barker

net: miiphybb: Convert ifdef DEBUG to debug()

2025-02-04T22:34:37Z

Replace ifdeffery with plain debug() function call. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Paul Barker

net: mediatek: fix coding style of AN8855 switch driver

2025-01-31T17:29:01Z

This patch fixed the following coding style suggested by checkpatch.pl: 1. Use tab instead of space 2. Use BIT() instead of << 3. Use mdelay for long time delay 4. Remove useless parenthesises Signed-off-by: Weijie Gao

net: phy: Add RGMII RX/TX delay handling to DP83822 PHY

2025-01-31T01:28:33Z

The TI DP83822 does have support for configurable RGMII RX/TX clock shift, add support for parsing DT properties which describe the RX/TX clock shift configuration and configuration of the matching bits in RCSR register. The shift is only configurable on DP83822, the other PHYs supported by this PHY driver, namely DP83825/DP83826 variants, do not implement this functionality and the RCSR bits used to configure the clock shift are missing from those PHYs. The shift is configurable separately for RX and TX path. Each path can either enable the shift or disable the shift using single bit. In case the shift is disabled, a delay of 0ns is added to the path, otherwise a delay of 3.5ns is added to the path. Note that the two RCSR bits 11 and 12 have inverted logic, RCSR bit 12 enables RX internal shift when SET, while RCSR bit 11 enables TX shift when UNSET. Signed-off-by: Marek Vasut

net: ravb: Staticize bb_miiphy functions

2025-01-29T21:52:23Z

These functions can be static as they are referenced only in this file. Make them static. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Paul Barker

net: miiphybb: configs: Drop CONFIG_BITBANGMII_MULTI

2025-01-29T21:52:23Z

It seems that every remaining system which enables BITBANGMII also enables BITBANGMII_MULTI . Remove the BITBANGMII_MULTI symbol and assume it is always enabled. This allows removal of a bit of legacy code. No functional change intended. Signed-off-by: Marek Vasut Reviewed-by: Paul Barker

net: fsl_enetc: Enable optional ENETREF clock on i.MX95

2025-01-27T03:27:54Z

The ENETCv4 port DT nodes on i.MX95 may contain optional clock phandle to IMX95_CLK_ENETREF "ref" clock. These "ref" clock must be enabled for the ethernet to work. These "ref" clock are enabled after cold boot, but when the system booted Linux and rebooted, those "ref" clock might have been disabled in the process, which would make ethernet inoperable after reboot. Make sure those "ref" clock are always correctly enabled. Signed-off-by: Marek Vasut

Merge tag 'u-boot-socfpga-next-20250124' of https://source.denx.de/u-boot/custodians/u-boot-socfpga

2025-01-24T04:40:25Z

1. Bug fixed for doorbell in secure device manager mailbox driver 2. Enhancement on SoCFPGA dwc_eth_xgmac driver 3. Enhancement on DW MAC driver 4. Improved the error message and status for SoC64 device FPGA configuration driver 5. Updated existing watchdog in system manager to support new SM device

net: dwc_eth_xgmac_socfpga: Add support for distinct mac-mode and phy mode.

2025-01-24T01:56:22Z

This patch adds support for configuring the ethernet MAC mode independently from the PHY mode on our SoC FPGA board. Specifically, this is necessary for a scenario where the ethernet controller MAC is connected to the FPGA HVIO with a different GMII interface, and the FPGA output is routed to the PHY using a RGMII interface. To support this configuration, a mechanism is introduced to handle separate MAC mode settings, ensuring that the MAC controller and PHY can operate correctly with their respective interface modes. If mac-mode is not defined, the MAC mode will default to the PHY mode, ensuring compatibility and proper operation between the MAC and PHY. Signed-off-by: Boon Khai Ng Reviewed-by: Tien Fong Chee