<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/net, branch v2026.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>net: ravb: Configure CXR31 and CXR35 on rzg2l</title>
<updated>2025-12-23T14:35:34+00:00</updated>
<author>
<name>Mathieu Othacehe</name>
<email>othacehe@gnu.org</email>
</author>
<published>2025-12-10T14:17:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0c230a3a8ef46f76a730324f44da96c713088825'/>
<id>0c230a3a8ef46f76a730324f44da96c713088825</id>
<content type='text'>
As in Linux with d78c0ced60 ("net: ravb: Make write access to CXR35 first
before accessing other EMAC register"), configure CXR31 and CXR35 correctly
on rzg2. MII mode does not work correctly unless those registers are
properly configured.

Signed-off-by: Mathieu Othacehe &lt;othacehe@gnu.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
As in Linux with d78c0ced60 ("net: ravb: Make write access to CXR35 first
before accessing other EMAC register"), configure CXR31 and CXR35 correctly
on rzg2. MII mode does not work correctly unless those registers are
properly configured.

Signed-off-by: Mathieu Othacehe &lt;othacehe@gnu.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-socfpga-next-20251201' of https://source.denx.de/u-boot/custodians/u-boot-socfpga</title>
<updated>2025-12-01T16:37:45+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-12-01T16:37:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c6ee44b5573a90b0a3a36cf858954e04439ae632'/>
<id>c6ee44b5573a90b0a3a36cf858954e04439ae632</id>
<content type='text'>
This pull request delivers a broad set of improvements across the
SoCFPGA family, including Agilex5, Cyclone V, SoC64, and common code.
Key updates include refined boot flows, new driver enablement, handoff
tooling enhancements, and several stability fixes.

Highlights:

* Agilex5:
  - Enable FAT-based environment storage
  - MMC driver restores legacy clkmgr-based clock lookup
  - Cleanup of MMC raw mode enablement logic

* Cyclone V:
  - SPL FAT boot support and updated bootcmd sequence
  - Disable SPL SPI to prevent contention with FAT-based boot
  - New board handoff script and BSP generator tooling
  - Optimized Makefile support for SoCFPGA handoff workflows* New drivers:
  - Cadence xSPI driver with full protocol and command support
  - SPL enablement for DW APB GPIO controller

* Networking:
  - xgmac MDIO now supports Clause 45 read/write operations

* NAND / SoC64:
  - Enable ONFI detection in Denali NAND controller for SoC64 devices

* DTS and board updates:
  - Sync common SoCFPGA U-Boot DTS with kernel sources
  - Fixes for FPGA2SDRAM configuration and SoCFPGA boot stall behavior
  - Vining_FPGA migrated to the modern LED framework
  - Device tree relocation no longer forced off for Vining FPGA

* Tooling:
  - Introduces a new Python-based Cyclone V BSP generator
    covering EMIF, IOCSR, HPS, XML parsing, rendering, and documentation
    to simplify board enablement and handoff regeneration workflows

Overall, this series improves boot robustness, enhances xSPI and MDIO
capabilities, modernizes board support, and introduces new tooling to
streamline SoCFPGA handoff generation.

Pipelines test passing
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28569
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This pull request delivers a broad set of improvements across the
SoCFPGA family, including Agilex5, Cyclone V, SoC64, and common code.
Key updates include refined boot flows, new driver enablement, handoff
tooling enhancements, and several stability fixes.

Highlights:

* Agilex5:
  - Enable FAT-based environment storage
  - MMC driver restores legacy clkmgr-based clock lookup
  - Cleanup of MMC raw mode enablement logic

* Cyclone V:
  - SPL FAT boot support and updated bootcmd sequence
  - Disable SPL SPI to prevent contention with FAT-based boot
  - New board handoff script and BSP generator tooling
  - Optimized Makefile support for SoCFPGA handoff workflows* New drivers:
  - Cadence xSPI driver with full protocol and command support
  - SPL enablement for DW APB GPIO controller

* Networking:
  - xgmac MDIO now supports Clause 45 read/write operations

* NAND / SoC64:
  - Enable ONFI detection in Denali NAND controller for SoC64 devices

* DTS and board updates:
  - Sync common SoCFPGA U-Boot DTS with kernel sources
  - Fixes for FPGA2SDRAM configuration and SoCFPGA boot stall behavior
  - Vining_FPGA migrated to the modern LED framework
  - Device tree relocation no longer forced off for Vining FPGA

* Tooling:
  - Introduces a new Python-based Cyclone V BSP generator
    covering EMIF, IOCSR, HPS, XML parsing, rendering, and documentation
    to simplify board enablement and handoff regeneration workflows

Overall, this series improves boot robustness, enhances xSPI and MDIO
capabilities, modernizes board support, and introduces new tooling to
streamline SoCFPGA handoff generation.

Pipelines test passing
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28569
</pre>
</div>
</content>
</entry>
<entry>
<title>net: phy: broadcom: fix RGMII delays for BCM54210E</title>
<updated>2025-12-01T08:52:33+00:00</updated>
<author>
<name>Michael Walle</name>
<email>mwalle@kernel.org</email>
</author>
<published>2025-11-27T15:25:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7c1b99bd60185c24d2c78862c3345895ffcd1d71'/>
<id>7c1b99bd60185c24d2c78862c3345895ffcd1d71</id>
<content type='text'>
bcm54210e_config() configures the RGMII delays and then calls
bcm5461_config(). But the latter will do a PHY soft reset and thus
resets the delay settings again. Call bcm5461_config() first to fix it.

Fixes: cba79a1b2e11 ("net: phy: broadcom: add support for BCM54210E")
Signed-off-by: Michael Walle &lt;mwalle@kernel.org&gt;
Reviewed-by: Rafał Miłecki &lt;rafal@milecki.pl&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
bcm54210e_config() configures the RGMII delays and then calls
bcm5461_config(). But the latter will do a PHY soft reset and thus
resets the delay settings again. Call bcm5461_config() first to fix it.

Fixes: cba79a1b2e11 ("net: phy: broadcom: add support for BCM54210E")
Signed-off-by: Michael Walle &lt;mwalle@kernel.org&gt;
Reviewed-by: Rafał Miłecki &lt;rafal@milecki.pl&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: phy: dp83869: fix STRAP_OPMODE bitmask</title>
<updated>2025-12-01T08:52:33+00:00</updated>
<author>
<name>Thanh Quan</name>
<email>thanh.quan.xn@renesas.com</email>
</author>
<published>2025-10-27T14:03:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=85a7e45c3350afd9f7c17bb0bb2a47aa94be982d'/>
<id>85a7e45c3350afd9f7c17bb0bb2a47aa94be982d</id>
<content type='text'>
According to the TI DP83869HM datasheet Revision D (June 2025), section
7.6.1.41 STRAP_STS Register, the STRAP_OPMODE bitmask is bit [11:9].
Fix this.

In case the PHY is auto-detected via PHY ID registers, or not described
in DT, or, in case the PHY is described in DT but the optional DT property
"ti,op-mode" is not present, then the driver reads out the PHY functional
mode (RGMII, SGMII, ...) from hardware straps.

Currently, all upstream users of this PHY specify both DT compatible string
"ethernet-phy-id2000.a0f1" and ti,op-mode = &lt;DP83869_RGMII_COPPER_ETHERNET&gt;
property, therefore it seems no upstream users are affected by this bug.

The driver currently interprets bits [2:0] of STRAP_STS register as PHY
functional mode. Those bits are controlled by ANEG_DIS, ANEGSEL_0 straps
and an always-zero reserved bit. Systems that use RGMII-to-Copper functional
mode are unlikely to disable auto-negotiation via ANEG_DIS strap, or change
auto-negotiation behavior via ANEGSEL_0 strap. Therefore, even with this bug
in place, the STRAP_STS register content is likely going to be interpreted
by the driver as RGMII-to-Copper mode.

However, for a system with PHY functional mode strapping set to other mode
than RGMII-to-Copper, the driver is likely to misinterpret the strapping
as RGMII-to-Copper and misconfigure the PHY.

For example, on a system with SGMII-to-Copper strapping, the STRAP_STS
register reads as 0x0c20, but the PHY ends up being configured for
incompatible RGMII-to-Copper mode.

Fixes: f3e22eea815d ("net: phy: add TI DP83869HM ethernet driver")
Signed-off-by: Thanh Quan &lt;thanh.quan.xn@renesas.com&gt;
Signed-off-by: Hai Pham &lt;hai.pham.ud@renesas.com&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt; # Use FIELD_GET()
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
According to the TI DP83869HM datasheet Revision D (June 2025), section
7.6.1.41 STRAP_STS Register, the STRAP_OPMODE bitmask is bit [11:9].
Fix this.

In case the PHY is auto-detected via PHY ID registers, or not described
in DT, or, in case the PHY is described in DT but the optional DT property
"ti,op-mode" is not present, then the driver reads out the PHY functional
mode (RGMII, SGMII, ...) from hardware straps.

Currently, all upstream users of this PHY specify both DT compatible string
"ethernet-phy-id2000.a0f1" and ti,op-mode = &lt;DP83869_RGMII_COPPER_ETHERNET&gt;
property, therefore it seems no upstream users are affected by this bug.

The driver currently interprets bits [2:0] of STRAP_STS register as PHY
functional mode. Those bits are controlled by ANEG_DIS, ANEGSEL_0 straps
and an always-zero reserved bit. Systems that use RGMII-to-Copper functional
mode are unlikely to disable auto-negotiation via ANEG_DIS strap, or change
auto-negotiation behavior via ANEGSEL_0 strap. Therefore, even with this bug
in place, the STRAP_STS register content is likely going to be interpreted
by the driver as RGMII-to-Copper mode.

However, for a system with PHY functional mode strapping set to other mode
than RGMII-to-Copper, the driver is likely to misinterpret the strapping
as RGMII-to-Copper and misconfigure the PHY.

For example, on a system with SGMII-to-Copper strapping, the STRAP_STS
register reads as 0x0c20, but the PHY ends up being configured for
incompatible RGMII-to-Copper mode.

Fixes: f3e22eea815d ("net: phy: add TI DP83869HM ethernet driver")
Signed-off-by: Thanh Quan &lt;thanh.quan.xn@renesas.com&gt;
Signed-off-by: Hai Pham &lt;hai.pham.ud@renesas.com&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt; # Use FIELD_GET()
</pre>
</div>
</content>
</entry>
<entry>
<title>net: xgmac: Augment mdio read/write with cl-45 format support</title>
<updated>2025-12-01T05:54:04+00:00</updated>
<author>
<name>Nikunj Kela</name>
<email>nikunj.kela@sima.ai</email>
</author>
<published>2025-08-29T04:12:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b17c28488b31e44279b58e87fd838f601c393176'/>
<id>b17c28488b31e44279b58e87fd838f601c393176</id>
<content type='text'>
Currently, clause-22 format is supported. This change adds
support for clause-45 format.

Signed-off-by: Nikunj Kela &lt;nikunj.kela@sima.ai&gt;
Reviewed-by: Boon Khai Ng &lt;boon.khai.ng@altera.com&gt;
Tested-by: Boon Khai Ng &lt;boon.khai.ng@altera.com&gt;
Reviewed-by: Boon Khai Ng &lt;boon.khai.ng@altera.com&gt;
Tested-by: Boon Khai Ng &lt;boon.khai.ng@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently, clause-22 format is supported. This change adds
support for clause-45 format.

Signed-off-by: Nikunj Kela &lt;nikunj.kela@sima.ai&gt;
Reviewed-by: Boon Khai Ng &lt;boon.khai.ng@altera.com&gt;
Tested-by: Boon Khai Ng &lt;boon.khai.ng@altera.com&gt;
Reviewed-by: Boon Khai Ng &lt;boon.khai.ng@altera.com&gt;
Tested-by: Boon Khai Ng &lt;boon.khai.ng@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: ti: am65-cpsw-nuss: Ignore disabled ethernet ports</title>
<updated>2025-11-27T15:27:03+00:00</updated>
<author>
<name>Siddharth Vadapalli</name>
<email>s-vadapalli@ti.com</email>
</author>
<published>2025-11-21T13:21:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cc0ce9e8c494d20e75258584807aaaac4cc514bd'/>
<id>cc0ce9e8c494d20e75258584807aaaac4cc514bd</id>
<content type='text'>
Currently, the bind callback of the driver namely am65_cpsw_nuss_bind()
registers all ethernet ports including the ones that have been disabled
in the device-tree. Since the ports that have been disabled are ought to
be ignored, fix the implementation to register only the enabled ports as
indicated by their 'status' in their respective device-tree node.

Fixes: 3943531a5468 ("net: ti: am65-cpsw-nuss: Define bind method for CPSW driver")
Reported-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
Closes: https://patch.msgid.link/8b4ac072-125c-493b-b12a-f0a4e9d56e7e@phytec.de
Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently, the bind callback of the driver namely am65_cpsw_nuss_bind()
registers all ethernet ports including the ones that have been disabled
in the device-tree. Since the ports that have been disabled are ought to
be ignored, fix the implementation to register only the enabled ports as
indicated by their 'status' in their respective device-tree node.

Fixes: 3943531a5468 ("net: ti: am65-cpsw-nuss: Define bind method for CPSW driver")
Reported-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
Closes: https://patch.msgid.link/8b4ac072-125c-493b-b12a-f0a4e9d56e7e@phytec.de
Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: axi_emac: Fix compilation warnings</title>
<updated>2025-11-19T08:28:50+00:00</updated>
<author>
<name>Sai Varun Venkatapuram</name>
<email>saivarun.venkatapuram@amd.com</email>
</author>
<published>2025-11-07T10:13:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2e86581d055bff8335d7e43d58617db16f11384f'/>
<id>2e86581d055bff8335d7e43d58617db16f11384f</id>
<content type='text'>
Fix compiler warnings about casting integers to pointers of different
sizes by using uintptr_t as intermediate type. This ensures proper
type conversion across 32-bit and 64-bit architectures.

Signed-off-by: Sai Varun Venkatapuram &lt;saivarun.venkatapuram@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/11b1d9b1a5589d06cff724e807832f366794c075.1762510401.git.michal.simek@amd.com
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix compiler warnings about casting integers to pointers of different
sizes by using uintptr_t as intermediate type. This ensures proper
type conversion across 32-bit and 64-bit architectures.

Signed-off-by: Sai Varun Venkatapuram &lt;saivarun.venkatapuram@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/11b1d9b1a5589d06cff724e807832f366794c075.1762510401.git.michal.simek@amd.com
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge patch series "arm: airoha: add support for en7523 based boards"</title>
<updated>2025-11-07T22:45:09+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-11-07T22:04:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5e5b630eef2eecfe898b2ce3e719a6dc79211569'/>
<id>5e5b630eef2eecfe898b2ce3e719a6dc79211569</id>
<content type='text'>
Mikhail Kshevetskiy &lt;mikhail.kshevetskiy@iopsys.eu&gt; says:

This patch series adds basic support for the boards based on Airoha
EN7523/EN7529/EN7562 SoCs. Due to ATF restrictions these boards are
able to run 32-bit OS only.

This patch series adds support for the following hardware:
 * console UART
 * ethernet controller/switch
 * spinand flash (in non-dma mode)

The following issues may be expected:
 * Extra slow UBI attaching in U-Boot (up to 20 sec with fastmap enabled).
   This is caused by the lack of DMA support in the U-Boot airoha-snfi driver.
 * Linux airoha-snfi driver in some cases might damage you flash data
   (see: https://lore.kernel.org/lkml/20251012121707.2296160-15-mikhail.kshevetskiy@iopsys.eu/)
 * Latest linux kernel is recommended to properly support flashes
   with more than one plane per lun
   (see: https://lore.kernel.org/lkml/20251012121707.2296160-7-mikhail.kshevetskiy@iopsys.eu/)
 * It's NOT recommended to use flashes working in continuous mode because
   U-Boot airoha-snfi driver does not support such flashes properly.

The patches was tested on the board:
 - SoC: Airoha EN7562
 - RAM: 512 MB
 - SPI NAND: 4 Gbit, made by Toshiba
 - Linux boot: was NOT tested

The U-Boot was chain-loaded from the running U-Boot. Airoha ATF-2.3 does
not allow easily chain-loading of U-Boot from U-Boot, so a special FIT
image (mimic linux kernel) was created

1) Create u-boot.its file with the following contents:

=== cut here ===
/dts-v1/;

/ {
	description = "ARM OpenWrt FIT (Flattened Image Tree)";
	#address-cells = &lt;1&gt;;

	images {
		u-boot-ram {
			description = "OpenWrt U-Boot RAM image";
			data = /incbin/("u-boot.bin.lzma");
			type = "kernel";
			arch = "arm";
			os = "linux";
			compression = "lzma";
			load = &lt;0x81e00000&gt;;
			entry = &lt;0x81e00000&gt;;
			hash@1 {
				algo = "crc32";
			};
			hash@2 {
				algo = "sha1";
			};
		};

		fdt-1 {
			description = "OpenWrt device tree blob";

			data = /incbin/("dts/upstream/src/arm/airoha/en7523-evb.dtb");
			type = "flat_dt";

			arch = "arm";
			compression = "none";
			hash@1 {
				algo = "crc32";
			};
			hash@2 {
				algo = "sha1";
			};
		};
	};

	configurations {
		default = "config-ram-uboot";
		config-ram-uboot {
			description = "OpenWrt RAM U-Boot";
			kernel = "u-boot-ram";
			fdt = "fdt-1";
		};
	};
};
==================

2) Create u-boot.itb image to chain-load new u-boot from the old one

  lzma_alone e u-boot.bin u-boot.bin.lzma
  mkimage -f u-boot.its u-boot.itb

3) Load new u-boot from the old one

  U-Boot&gt; tftpboot u-boot.itb &amp;&amp; bootm

Link: https://lore.kernel.org/r/20251101004503.2379529-1-mikhail.kshevetskiy@iopsys.eu
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Mikhail Kshevetskiy &lt;mikhail.kshevetskiy@iopsys.eu&gt; says:

This patch series adds basic support for the boards based on Airoha
EN7523/EN7529/EN7562 SoCs. Due to ATF restrictions these boards are
able to run 32-bit OS only.

This patch series adds support for the following hardware:
 * console UART
 * ethernet controller/switch
 * spinand flash (in non-dma mode)

The following issues may be expected:
 * Extra slow UBI attaching in U-Boot (up to 20 sec with fastmap enabled).
   This is caused by the lack of DMA support in the U-Boot airoha-snfi driver.
 * Linux airoha-snfi driver in some cases might damage you flash data
   (see: https://lore.kernel.org/lkml/20251012121707.2296160-15-mikhail.kshevetskiy@iopsys.eu/)
 * Latest linux kernel is recommended to properly support flashes
   with more than one plane per lun
   (see: https://lore.kernel.org/lkml/20251012121707.2296160-7-mikhail.kshevetskiy@iopsys.eu/)
 * It's NOT recommended to use flashes working in continuous mode because
   U-Boot airoha-snfi driver does not support such flashes properly.

The patches was tested on the board:
 - SoC: Airoha EN7562
 - RAM: 512 MB
 - SPI NAND: 4 Gbit, made by Toshiba
 - Linux boot: was NOT tested

The U-Boot was chain-loaded from the running U-Boot. Airoha ATF-2.3 does
not allow easily chain-loading of U-Boot from U-Boot, so a special FIT
image (mimic linux kernel) was created

1) Create u-boot.its file with the following contents:

=== cut here ===
/dts-v1/;

/ {
	description = "ARM OpenWrt FIT (Flattened Image Tree)";
	#address-cells = &lt;1&gt;;

	images {
		u-boot-ram {
			description = "OpenWrt U-Boot RAM image";
			data = /incbin/("u-boot.bin.lzma");
			type = "kernel";
			arch = "arm";
			os = "linux";
			compression = "lzma";
			load = &lt;0x81e00000&gt;;
			entry = &lt;0x81e00000&gt;;
			hash@1 {
				algo = "crc32";
			};
			hash@2 {
				algo = "sha1";
			};
		};

		fdt-1 {
			description = "OpenWrt device tree blob";

			data = /incbin/("dts/upstream/src/arm/airoha/en7523-evb.dtb");
			type = "flat_dt";

			arch = "arm";
			compression = "none";
			hash@1 {
				algo = "crc32";
			};
			hash@2 {
				algo = "sha1";
			};
		};
	};

	configurations {
		default = "config-ram-uboot";
		config-ram-uboot {
			description = "OpenWrt RAM U-Boot";
			kernel = "u-boot-ram";
			fdt = "fdt-1";
		};
	};
};
==================

2) Create u-boot.itb image to chain-load new u-boot from the old one

  lzma_alone e u-boot.bin u-boot.bin.lzma
  mkimage -f u-boot.its u-boot.itb

3) Load new u-boot from the old one

  U-Boot&gt; tftpboot u-boot.itb &amp;&amp; bootm

Link: https://lore.kernel.org/r/20251101004503.2379529-1-mikhail.kshevetskiy@iopsys.eu
</pre>
</div>
</content>
</entry>
<entry>
<title>net: airoha: add support for airoha en7523 SoC family</title>
<updated>2025-11-07T22:00:59+00:00</updated>
<author>
<name>Mikhail Kshevetskiy</name>
<email>mikhail.kshevetskiy@iopsys.eu</email>
</author>
<published>2025-11-01T00:44:59+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=251e27fcc209f840b4f33615f89e4859ddb44242'/>
<id>251e27fcc209f840b4f33615f89e4859ddb44242</id>
<content type='text'>
Add support for Ethernet controller present in Airoha en7523/en7529/en7562.

Signed-off-by: Mikhail Kshevetskiy &lt;mikhail.kshevetskiy@iopsys.eu&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for Ethernet controller present in Airoha en7523/en7529/en7562.

Signed-off-by: Mikhail Kshevetskiy &lt;mikhail.kshevetskiy@iopsys.eu&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>net: airoha: unify code using SCU regmap helper</title>
<updated>2025-11-07T22:00:59+00:00</updated>
<author>
<name>Mikhail Kshevetskiy</name>
<email>mikhail.kshevetskiy@iopsys.eu</email>
</author>
<published>2025-11-01T00:44:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=801a84b1a46ac70f49772a2c7069a33cd30cf720'/>
<id>801a84b1a46ac70f49772a2c7069a33cd30cf720</id>
<content type='text'>
This allow us remove some an7581/an7583 specific code and use a common
code instead.

Signed-off-by: Mikhail Kshevetskiy &lt;mikhail.kshevetskiy@iopsys.eu&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This allow us remove some an7581/an7583 specific code and use a common
code instead.

Signed-off-by: Mikhail Kshevetskiy &lt;mikhail.kshevetskiy@iopsys.eu&gt;
</pre>
</div>
</content>
</entry>
</feed>
