u-boot.git/drivers/net, branch v2026.04-rc2

Merge tag 'net-20260209' of https://source.denx.de/u-boot/custodians/u-boot-net

2026-02-09T14:28:01Z

Pull request net-20260209. net: - airoha: mdio support for the switch - phy: mscc: allow RGMII with internal delay for the VSC8541 - dwc_eth_qos: Update tail pointer handling net-legacy: - Stop conflating return value with file size in net_loop() net-lwip: - wget: rework the '#' printing - tftp: add support of tsize option to client

net: fec_mxc: Add support for i.MX91

2026-02-06T23:29:30Z

The i.MX91 SoC reuses the ENET FEC from i.MX93. Add all required driver checks to make it work also on the i.MX91 based platforms. Signed-off-by: Primoz Fiser

net: phy: mscc: allow RGMII with internal delay for the VSC8541

2026-02-06T15:42:45Z

Add the missing RGMII modes with internal delay for the VSC8541. Fixes: a5fd13ad1913 ("net: phy: MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541") Signed-off-by: Charles Perry

net: mdio-mt7531-mmio: fix switch regs initialization

2026-02-06T15:42:45Z

mdio is a child node of the switch, so to get switch base address we need to lookup for a parent node Signed-off-by: Mikhail Kshevetskiy

net: airoha_eth: use proper switch node for en7523 case

2026-02-06T15:42:45Z

Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load") uses "airoha,en7581-switch" dts node for finding MDIO childs. This is wrong for EN7523 SoC. The correct node name should be used instead. Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load") Signed-off-by: Mikhail Kshevetskiy

net: airoha_eth: fix mdio binding to switch device

2026-02-06T15:42:45Z

Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load") refers to non-present CONFIG_MDIO_MT7531 and non-present "mt7531-mdio" driver. It should use CONFIG_MDIO_MT7531_MMIO and "mt7531-mdio-mmio" instead. Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load") Signed-off-by: Mikhail Kshevetskiy

net: dwc_eth_qos: Define more of the unused MAC regs

2026-02-06T15:42:45Z

Multicast and Broadcast Queue Enable and Promiscuous Mode Enable bits are currently written to "unused" registers using magic values. Define more of the "unused" MAC regs based on information in the DesignWare Cores Ethernet Quality-of-Service databook. Signed-off-by: Jonas Karlman

net: dwc_eth_qos: Start DMA and MAC after tail pointers are initialized

2026-02-06T15:42:45Z

The DesignWare Cores Ethernet Quality-of-Service databook state that receive and transmit descriptor list address and also transmit and receive tail pointer registers should be initialized before the receive and transmit DMAs are started. It also state to enable the MAC receiver only after the DMA is active. Otherwise, received frames can fill the Rx FIFO and overflow. Move the activation of receive and transmit DMA and MAC receiver until after tail pointer registers have been initialized. Signed-off-by: Jonas Karlman

net: dwc_eth_qos: Initialize the transmit tail pointer in eqos_start()

2026-02-06T15:42:45Z

The DesignWare Cores Ethernet Quality-of-Service databook state that descriptors up to one location less than the one indicated by the descriptor tail pointer are owned by the DMA. The DMA continues to process the descriptors until the following condition occurs: Current Descriptor Pointer == Descriptor Tail Pointer The DMA goes into suspend mode when this condition occurs, and updating the tail pointer resume the DMA processing. Configure the transmit tail pointer to the first (current) descriptor pointer so that the tail pointer is a valid address instead of being initialized to NULL when transmit DMA is started. Also update the receive tail pointer comment to state that by pointing to the last descriptor we are actually implying that all receive descriptors are owned by and can be processed by the DMA. Signed-off-by: Jonas Karlman

net: dwc_eth_qos: Use lower_32_bits() for tail pointers

2026-02-06T15:42:45Z

The DesignWare Cores Ethernet Quality-of-Service databook state that the descriptor address from the start to the end of the ring must not cross the 4GB boundary. Use lower_32_bits() to write the lower 32 bits of descriptor addresses, including the 32-bit tail pointers, consistently. No functional change is intended. Signed-off-by: Jonas Karlman