u-boot.git/drivers/net, branch v2026.07

net: mtk_eth: select LMB_LIMIT_DMA_BELOW_RAM_TOP

2026-06-24T15:06:16Z

Default to CONFIG_LMB_LIMIT_DMA_BELOW_RAM_TOP=y when MEDIATEK_ETH is enabled. The MediaTek Ethernet controller can only access the first 4GB of RAM when DMA is used. Link: https://patch.msgid.link/20260615-mtk-fix-ram-size-v2-2-f72cfc52ce58@baylibre.com Signed-off-by: David Lechner

net: airoha_eth: fix mt7531 mdio related initialization bug

2026-06-23T11:13:16Z

Private data isn't ready during bind time. The call of dev_get_priv() function will return NULL. Thus we can't save mdio device pointer and use it later during probe. To solve an issue, we will move mt7531 mdio device binding to the probing function of 'airoha-eth' driver. All GDM ports (except of GDM1) are connected directly to their PHYs, so corresponding mdio bus will be automatically probed during PHY setup. GDM1 ports differ from other GDM ports. It connected to the airoha switch device. The mt7531 mdio bus is used to manage link state of airoha switch device ports (LAN ports 1-4 corresponds to PHYs 0x09-0x0C). Therefore, manual probing of mt7531 mdio bus is required to be able set/query states of corresponding LAN ports. Fixes: 96d9e7c46425 ("net: airoha: use mt7531 mdio for GDM1") Signed-off-by: Mikhail Kshevetskiy

net: ti: icssg: Fix portname buffer overflow

2026-06-03T15:22:24Z

portname consists of dev->parent->name ("icssg0-eth", "icssg1-eth", or "ethernet") and dev->name is the port node name ("port@0" or "port@1"). Every board DTS in the repository produces a string that overflows the buffer: "icssg1-eth-port@0" 17 chars + NUL = 18 bytes (AM642 EVM, IoT2050) "ethernet-port@0" 15 chars + NUL = 16 bytes (SR-SOM, phyboard) This commits increases portname to 64 bytes and replaces sprintf by snprintf so that any future DT node name cannot overflow it regardless of length. Signed-off-by: Francois Berder Reviewed-by: Jerome Forissier

net: phy: mscc: add support for the VSC8572

2026-05-06T09:07:22Z

This is similar to the VSC8574 according to the Linux commit that adds support for it [1]. This was tested on an HX1000 board with SGMII (PIC64-HX SoC which has a GEM MAC). [1]: https://lore.kernel.org/all/dfabe39a52efcd2cfff9358f271b8673143503b8.1480497966.git.neill.whillans@codethink.co.uk/ Signed-off-by: Charles Perry Reviewed-by: Manikandan Muralidharan

net: macb: add gigabit implementation for fixed-link

2026-05-06T09:07:22Z

A fixed gigabit link on a non-gigabit controller is only rejected during PHY init (even though there is no PHY to init), because, on device-tree parsing, the controller is not probed, and it is still unknown whether it is gigabit-capable. This code was only tested on emulator with a full-duplex RGMII interface, but is expected to work in GMII or half-duplex as well. Signed-off-by: Christian DREHER

net: macb: do not set user_io when it does not exist

2026-05-06T09:07:22Z

Cadence Ethernet MAC has a feature named user_io, which provides some input and some output signals for arbitrary purpose in the SoC. From the driver code, I understand that, on Atmel SoC, it is used to drive the PHY mode. At least on Cadence IP7014 r1p12, this feature is optional, and I am working on a SoC that does not instantiate it. The presence of this feature is advertised in DCFG1, this patch merely disables the access to the user_io register based on this information. I did not apply this change to the non-gigabit capable versions of the IP, as I do not have documentation for them, and a new non-gigabit instance is unlikely to appear. I prefer avoiding regressions on old systems. Signed-off-by: Christian DREHER

net: macb: use SA1 for MAC filtering on GEM

2026-05-06T09:07:22Z

The MACB uses specific address registers (SA Top and Bottom) to filter source or destination MAC addresses. On the Gigabit Ethernet version, SA1B is @0x88. On the non-GEM version, SA1B is @0x98. Before this commit, the code was always writing 0x98. By chance, on GEM, this is the address of SA3B, allowing the driver to work anyway. The motivation for this change is to be able to use the driver on an instance of the GEM with less than 4 SA registers. Signed-off-by: Christian DREHER

net: macb: include arch/clk.h only when necessary

2026-05-06T09:07:22Z

It does not exist in my setup (an on-going arm64 SoC), and removing it does not cause any missing declaration, but some code called when CONFIG_CLK is missing calls get_macb_pclk_rate, which is only defined in arch/arm/mach-at91/include/mach/clk.h Signed-off-by: Christian DREHER

net: phy: adin: add support for the ADIN1200 phy

2026-05-06T09:07:22Z

The ADIN1200 chip is register compatible with the ADIN1300, but only supports 10/100 Mbit. Signed-off-by: Rasmus Villemoes

net: phy: airoha: air_en8811: use standard rx-polarity/tx-polarity properties

2026-05-06T09:07:22Z

Replace the proprietary airoha,pnswap-rx / airoha,pnswap-tx boolean device tree properties with the standard rx-polarity and tx-polarity properties defined in phy-common-props.yaml. Backward compatibility is maintained by reading the legacy boolean properties first and passing them as the default_pol argument to phy_get_rx/tx_polarity(). If the standard properties are absent the legacy values are used transparently, so existing device trees remain functional without modification. Link: https://git.kernel.org/linus/66d8a334b57e64e43810623b3d88f0ce9745270b Signed-off-by: Lucien.Jheng