u-boot.git/drivers/nvme, branch v2021.01

nvme: Use only 32-bit accesses in nvme_writeq/nvme_readq

2021-01-04T14:10:16Z

There might be hardware configurations where 64-bit data accesses to NVMe registers are not supported properly. This patch removes the readq/writeq so always two 32-bit accesses are used to read/write 64-bit NVMe registers, similarly as it is done in Linux kernel. This patch fixes operation of NVMe devices on RPi4 Broadcom BCM2711 SoC based board, where the PCIe Root Complex, which is attached to the system through the SCB bridge. Even though the architecture is 64-bit the PCIe BAR is 32-bit and likely the 64-bit wide register accesses initiated by the CPU are not properly translated to a sequence of 32-bit PCIe accesses. nvme_readq(), for example, always returns same value in upper and lower 32-bits, e.g. 0x3c033fff3c033fff which lead to NVMe devices to fail probing. This fix is analogous to commit 8e2ab05000ab ("usb: xhci: Use only 32-bit accesses in xhci_writeq/xhci_readq"). Cc: Sylwester Nawrocki Cc: Nicolas Saenz Julienne Cc: Matthias Brugger Reviewed-by: Stefan Roese Reviewed-by: Bin Meng Signed-off-by: Stefan Agner

nvme: Invalidate dcache before submitting admin cmd

2020-06-23T18:43:23Z

This patch try to avoids eviction of dirty lines during DMA transfer. The code right now execute the following step: - allocate the buffer - start a dma operation using the non-coherent dma buffer - invalidate cache lines associated with the buffer - read the buffer This can lead to reading back not valid information, because the cache controller could evict dirty cache lines belonging to the buffer *after* the DMA operation has started to fill the DRAM. In order to avoid this, a new invalidation is required *before* starting the DMA operation. The patch just adds an invalidation before submitting the DMA command. Example below shows the nvme disk scan result without the following patch => nvme scan nvme_get_info_from_identify: nn = 544502629, vwc = 100, sn = dev_0T, mn = `�\�, fr = t_part, mdts = 105 So, invalidating the cache before submitting the admin command, fix the cpu read. Cc: André Przywara Reported-by: Suniel Mahesh Signed-off-by: Michael Trimarchi Signed-off-by: Jagan Teki Tested-by: Suniel Mahesh Reviewed-by: Bin Meng

common: Drop log.h from common header

2020-05-19T01:19:18Z

Move this header out of the common header. Signed-off-by: Simon Glass

common: Drop part.h from common header

2020-05-18T21:33:33Z

Move this uncommon header out of the common header. Signed-off-by: Simon Glass

dm: core: Create a new header file for 'compat' features

2020-02-06T02:33:46Z

At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass

common: Move ARM cache operations out of common.h

2019-12-02T23:24:58Z

These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass Reviewed-by: Daniel Schwierzeck Reviewed-by: Tom Rini

common: Move get_ticks() function out of common.h

2019-12-02T23:23:13Z

This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass Reviewed-by: Tom Rini

nvme: use page-aligned buffer for identify command

2019-10-31T11:22:53Z

Change the stack-allocated buffer for the identification command to explicitly allocate page-aligned buffers. Even though the spec seems to allow having admin queue commands on non page-aligned buffers, it seems to not be possible on my i.MX8MQ board with a a Silicon Power P34A80. Since all of the NVMe drivers I have seen always do admin commands on a page-aligned buffer, which does work on my system, it makes sense for us to do that as well. Signed-off-by: Patrick Wildt Reviewed-by: Bin Meng

nvme: flush dcache on both r/w, and the prp list

2019-10-31T11:22:53Z

It's possible that the data cache for the buffer still holds data to be flushed to memory, since the buffer was probably used as stack before. Thus we need to make sure to flush it also on reads, since it's possible that the cache is automatically flused to memory after the NVMe DMA transfer happened, thus overwriting the NVMe transfer's data. Also add a missing dcache flush for the prp list. Signed-off-by: Patrick Wildt Reviewed-by: Bin Meng

nvme: add accessor to namespace id and eui64

2019-10-06T14:02:37Z

This adds a function which can be used by e.g. EFI to retrieve the namespace identifier and EUI64. For that it adds the EUI64 to its driver internal namespace structure and copies the EUI64 during namespace identification. Signed-off-by: Patrick Wildt Tested-by: Heinrich Schuchardt Reviewed-by: Bin Meng