<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/pch, branch v2017.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>dm: Use dm_scan_fdt_dev() directly where possible</title>
<updated>2016-07-27T20:15:54+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-05T23:10:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=911954859d6dece49c3e4835faea004cfe392506'/>
<id>911954859d6dece49c3e4835faea004cfe392506</id>
<content type='text'>
Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()</title>
<updated>2016-07-27T20:15:07+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-05T23:10:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2e3f1ff63f50f36e74d46f939823241856ebf1bd'/>
<id>2e3f1ff63f50f36e74d46f939823241856ebf1bd</id>
<content type='text'>
This new function is more convenient for callers, and handles pre-relocation
situations automatically.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This new function is more convenient for callers, and handles pre-relocation
situations automatically.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: pch9: Implement get_io_base op</title>
<updated>2016-02-05T04:47:21+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4f106bc8becc194057cd306f9188b1393b7df558'/>
<id>4f106bc8becc194057cd306f9188b1393b7df558</id>
<content type='text'>
IO_BASE is only seen on PCH9 device, implement the get_io_base op.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
IO_BASE is only seen on PCH9 device, implement the get_io_base op.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pch: Add get_io_base op</title>
<updated>2016-02-05T04:47:21+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=79d4eb627cffbc3ab7cefdd623fa39fefaaedbe7'/>
<id>79d4eb627cffbc3ab7cefdd623fa39fefaaedbe7</id>
<content type='text'>
On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: pch: Implement get_gpio_base op</title>
<updated>2016-02-05T04:47:21+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ec2af6f82d4ee07fa19877e2bb2e5c80d8d6962b'/>
<id>ec2af6f82d4ee07fa19877e2bb2e5c80d8d6962b</id>
<content type='text'>
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pch: Add get_gpio_base op</title>
<updated>2016-02-05T04:47:21+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=384980c687ca38c028bdf40f59a38b3f52105884'/>
<id>384980c687ca38c028bdf40f59a38b3f52105884</id>
<content type='text'>
x86 GPIO registers are accessed via I/O port whose base address is
configured in a PCI configuration register on the PCH device. Add
an op get_gpio_base to get the GPIO base address from PCH.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
x86 GPIO registers are accessed via I/O port whose base address is
configured in a PCI configuration register on the PCH device. Add
an op get_gpio_base to get the GPIO base address from PCH.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pch: Rename get_sbase op to get_spi_base</title>
<updated>2016-02-05T04:47:21+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3e389d8ba666c5c2ad42021c2087630c1e412954'/>
<id>3e389d8ba666c5c2ad42021c2087630c1e412954</id>
<content type='text'>
Spell out 'sbase' to 'spi_base' so that it looks clearer.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Spell out 'sbase' to 'spi_base' so that it looks clearer.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pch: Remove pch_get_version op</title>
<updated>2016-02-05T04:47:21+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d02be99e6774b99c27b7d4304865c7f45e1ac4b4'/>
<id>d02be99e6774b99c27b7d4304865c7f45e1ac4b4</id>
<content type='text'>
pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller driver was updated to not get such info
from pch, the pch_get_version op is useless now.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller driver was updated to not get such info
from pch, the pch_get_version op is useless now.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: x86: Add a driver for Intel PCH9</title>
<updated>2016-01-24T04:07:17+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-19T03:19:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=81afac123896cdd560411f78f673d5bdccbcafbb'/>
<id>81afac123896cdd560411f78f673d5bdccbcafbb</id>
<content type='text'>
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH9.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH9.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: x86: Add a driver for Intel PCH7</title>
<updated>2016-01-24T04:07:17+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-19T03:19:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1ff4f321b69950acca1b06daed89d872a52a337c'/>
<id>1ff4f321b69950acca1b06daed89d872a52a337c</id>
<content type='text'>
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
