u-boot.git/drivers/pci/Makefile, branch master Unnamed repository; edit this file 'description' to name the repository. pci: Remove pcie_intel_fpga driver 2025-10-08T19:54:58+00:00 Tom Rini trini@konsulko.com 2025-09-25T20:43:14+00:00 d40eae0e270f50e6e9b99d7bca334bb87bc28f70 This driver has never been enabled by a platform since introduction and does not currently compile. Remove it. Signed-off-by: Tom Rini <trini@konsulko.com> 
This driver has never been enabled by a platform since introduction and
does not currently compile. Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
pci: pcie-rcar-gen4: Add Renesas R-Car Gen4 DW PCIe controller driver 2025-06-27T14:25:56+00:00 Marek Vasut marek.vasut+renesas@mailbox.org 2025-06-17T08:16:31+00:00 be3dd0dc2fd9020fa19cd96ea82753315f4084b0 Add R-Car Gen4 PCIe controller support for host mode. This controller is based on Synopsys DesignWare PCIe. However, this particular controller has a number of vendor-specific registers, and as such, requires initialization code, including PHY firmware loading. The PHY firmware loading is implemented in an entirely generic manner, by calling a firmware loading script, which the user can configure in a way they require. This provides the user with flexibility of loading the PCIe firmware from whichever storage device they need to load it from. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> 
Add R-Car Gen4 PCIe controller support for host mode.

This controller is based on Synopsys DesignWare PCIe. However, this
particular controller has a number of vendor-specific registers, and as
such, requires initialization code, including PHY firmware loading.

The PHY firmware loading is implemented in an entirely generic manner,
by calling a firmware loading script, which the user can configure in
a way they require. This provides the user with flexibility of loading
the PCIe firmware from whichever storage device they need to load it
from.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
pci: Add support for Qualcomm PCIe controller 2025-01-22T15:43:54+00:00 Neil Armstrong neil.armstrong@linaro.org 2024-11-25T09:46:17+00:00 5b7ec7fb4437e3e9b50127114a59796a90c1681a Add support for the PCIe busses on Qualcomm platforms, by using the pcie_dw_common infrastructure. The driver is based on the Linux driver but only supporting the "1_9_0" and compatible platforms like: - sa8540p - sc7280 - sc8180x - sc8280xp - sdm845 - sdx55 - sm8150 - sm8250 - sm8350 - sm8450 - sm8550 - sm8650 - x1e80100 But it has only been tested on: - sc7280 - sm8550 - sm8650 - x1e80100 It supports setting the IOMMU SID table for supported platforms. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241125-topic-pcie-controller-v1-2-45c20070dd53@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> 
Add support for the PCIe busses on Qualcomm platforms,
by using the pcie_dw_common infrastructure.

The driver is based on the Linux driver but only supporting
the "1_9_0" and compatible platforms like:
- sa8540p
- sc7280
- sc8180x
- sc8280xp
- sdm845
- sdx55
- sm8150
- sm8250
- sm8350
- sm8450
- sm8550
- sm8650
- x1e80100

But it has only been tested on:
- sc7280
- sm8550
- sm8650
- x1e80100

It supports setting the IOMMU SID table for supported platforms.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-controller-v1-2-45c20070dd53@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
pci: Add TI K3 Cadence PCIe Controller 2024-10-21T23:51:51+00:00 Siddharth Vadapalli s-vadapalli@ti.com 2024-10-14T05:39:23+00:00 59ad54800986668c73e3744bf9425c6946bf73bc Add support for the Cadence PCIe Controller present on TI's K3 SoCs. This driver is an adaptation of the Linux driver. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> 
Add support for the Cadence PCIe Controller present on TI's K3 SoCs.
This driver is an adaptation of the Linux driver.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
pci: mediatek: add PCIe controller support for filogic silicon 2024-07-08T17:45:50+00:00 John Crispin john@phrozen.org 2024-06-24T21:03:28+00:00 1a75300d94387598fff4e53abe36c25d16a105ae Add MediaTek GEN3 PCIe controller support for filogic silicon. This is adapted from the Linux version of the driver. Signed-off-by: John Crispin <john@phrozen.org> [ fix minor problems, fix checkpatch errors ] Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> 
Add MediaTek GEN3 PCIe controller support for filogic silicon.
This is adapted from the Linux version of the driver.

Signed-off-by: John Crispin <john@phrozen.org>
[ fix minor problems, fix checkpatch errors ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
pci: Add DW PCIe controller support for iMX8MP SoC 2024-03-24T16:35:59+00:00 Sumit Garg sumit.garg@linaro.org 2024-03-21T14:55:03+00:00 d56d49370f86b9ee2425ef156ad1d5cf7c3676fd pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is tied to quite old port of pcie_designware driver from Linux which suffices only iMX6 specific needs. But currently we have the common DWC specific bits which alligns pretty well with DW PCIe controller on iMX8MP SoC. So lets reuse those common bits instead as a new driver for iMX8 SoCs. It should be fairly easy to add support for other iMX8 variants to this driver. iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we can reuse the generic PHY infrastructure to power on PCIe PHY. Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> 
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.

But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.

iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.

Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
pci: ftpci100: add new driver implementation 2023-08-14T21:55:53+00:00 Sergei Antonov saproj@gmail.com 2023-07-30T18:17:09+00:00 852467de92c38c6c5b9338dd75989e306461dd08 Add a new DM driver supporting FTPCI100 IP used in SoC designs. This implementation is not based on the old non-DM ftpci100 code dropped from U-Boot. Enable the driver in sandbox_defconfig to test compilability. Signed-off-by: Sergei Antonov <saproj@gmail.com> 
Add a new DM driver supporting FTPCI100 IP used in SoC designs.
This implementation is not based on the old non-DM ftpci100 code
dropped from U-Boot.

Enable the driver in sandbox_defconfig to test compilability.

Signed-off-by: Sergei Antonov <saproj@gmail.com>
starfive: pci: Add StarFive JH7110 pcie driver 2023-08-02T03:02:32+00:00 Mason Huo mason.huo@starfivetech.com 2023-07-25T09:46:48+00:00 7870a05581243b510f6a1feedce1243ddcd49637 Add pcie driver for StarFive JH7110, Also add PLDA PCIe controller common driver functions. Several devices are tested: a) M.2 NVMe SSD b) Realtek 8169 Ethernet adapter. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> 
Add pcie driver for StarFive JH7110, Also add PLDA
PCIe controller common driver functions.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Acked-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
PCI: zynqmp: Add ZynqMP NWL PCIe root port driver 2023-06-12T11:25:02+00:00 Stefan Roese sr@denx.de 2023-05-25T09:49:18+00:00 2f5ad77cfead72b0e5156a7cc527b2f9eabde63e This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP NWL PCIe Bridge as root port. The driver source is partly copied from the Linux PCI driver and modified to enable usage in U-Boot (e.g. simplified and interrupt support removed). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Pali Rohár <pali@kernel.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> Acked-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20230525094918.111949-1-sr@denx.de Signed-off-by: Michal Simek <michal.simek@amd.com> 
This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP
NWL PCIe Bridge as root port. The driver source is partly copied from
the Linux PCI driver and modified to enable usage in U-Boot (e.g.
simplified and interrupt support removed).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Pali Rohár <pali@kernel.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/20230525094918.111949-1-sr@denx.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
sh4: Drop unused pci_sh7780 driver 2023-02-07T19:33:49+00:00 Simon Glass sjg@chromium.org 2023-02-01T20:20:08+00:00 295ae34c075d35e807bd61953d9418da89cbd554 This is not used. Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org> 
This is not used. Drop the driver and Kconfig option.

Signed-off-by: Simon Glass <sjg@chromium.org>