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<title>u-boot.git/drivers/pci/Makefile, branch v2015.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci/Makefile?h=v2015.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci/Makefile?h=v2015.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2014-12-18T20:19:20Z</updated>
<entry>
<title>pci: tegra: Add Tegra PCIe driver</title>
<updated>2014-12-18T20:19:20Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:12Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f315828b0d31cac2559af626f75bcb7f5a0ac524'/>
<id>urn:sha1:f315828b0d31cac2559af626f75bcb7f5a0ac524</id>
<content type='text'>
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.

This is based on the Linux kernel driver, originally submitted upstream
by Mike Rapoport.

Signed-off-by: Mike Rapoport &lt;mike@compulab.co.il&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm: ls102xa: Update PCIe dts node status</title>
<updated>2014-12-11T17:35:56Z</updated>
<author>
<name>Minghuan Lian</name>
<email>Minghuan.Lian@freescale.com</email>
</author>
<published>2014-10-31T05:43:44Z</published>
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<id>urn:sha1:da419027afe8336284f5db9867a880dfb3b3ab26</id>
<content type='text'>
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.

Signed-off-by: Minghuan Lian &lt;Minghuan.Lian@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
<entry>
<title>pci: Add general support for execution of video ROMs</title>
<updated>2014-11-25T14:11:14Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-15T03:56:33Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6854f87cbcad544dc07a02b96d358f81ca60c593'/>
<id>urn:sha1:6854f87cbcad544dc07a02b96d358f81ca60c593</id>
<content type='text'>
Some platforms don't have native code for dealing with their video
hardware. In some cases they use a binary blob to set it up and perform
required actions like setting the video mode. This approach is a hangover
from the old PC days where a ROM was provided and executed during startup.

Even now, these ROMs are supplied as a way to set up video. It avoids the
code for every video chip needing to be provided in the boot loader. But
it makes the video much less flexible - e.g. it is not possible to do
anything else while the video init is happening (including waiting hundreds
of milliseconds for display panels to start up).

In any case, to deal with this sad state of affairs, provide an API for
execution of x86 video ROMs, either natively or through emulation.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'</title>
<updated>2014-02-19T11:04:45Z</updated>
<author>
<name>Albert ARIBAUD</name>
<email>albert.u.boot@aribaud.net</email>
</author>
<published>2014-02-19T11:04:45Z</published>
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<id>urn:sha1:e7538fee991308c16f76f7eca2517089f2a30ff4</id>
<content type='text'>
</content>
</entry>
<entry>
<title>ARM: PCI: Remove the IXP PCI driver</title>
<updated>2014-02-06T01:51:52Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2014-01-27T23:18:20Z</published>
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<id>urn:sha1:c75692d3625c415e0e3fe982bd72a3300d828465</id>
<content type='text'>
The driver is no longer used, remove it.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Michael Schwingen &lt;michael@schwingen.org&gt;
Cc: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: mx6: Add PCI express driver</title>
<updated>2014-01-26T11:41:20Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2013-12-14T04:55:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e9be4292e4f32bcdfb88c19407da281e36447498'/>
<id>urn:sha1:e9be4292e4f32bcdfb88c19407da281e36447498</id>
<content type='text'>
Add PCIe driver for the Freescale i.MX6 SoC . This driver operates the
PCIe block in RC mode only, the EP mode is NOT supported. The driver is
tested with the Intel e1000 NIC driver.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Albert Aribaud &lt;albert.u.boot@aribaud.net&gt;
Cc: Eric Nelson &lt;eric.nelson@boundarydevices.com&gt;
Cc: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
</entry>
<entry>
<title>malta: support for coreFPGA6 boards</title>
<updated>2013-11-09T16:21:01Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2013-11-08T11:18:50Z</published>
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<id>urn:sha1:baf37f06c5cc51d2b9d71a2c83d5d92de60203a9</id>
<content type='text'>
This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.

Due to the PCI I/O base differing between Maltas using gt64120 &amp; msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.

Tested on:
  - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
    with and without an L2 cache.
  - QEMU.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</content>
</entry>
<entry>
<title>drivers: convert makefiles to Kbuild style</title>
<updated>2013-10-31T17:26:01Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2013-10-17T08:34:57Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=710f1d3d5f44731665a0d801d166c0f98c1de38e'/>
<id>urn:sha1:710f1d3d5f44731665a0d801d166c0f98c1de38e</id>
<content type='text'>
Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
</entry>
<entry>
<title>MIPS: qemu-malta: add PCI support</title>
<updated>2013-07-24T13:51:04Z</updated>
<author>
<name>Gabor Juhos</name>
<email>juhosg@openwrt.org</email>
</author>
<published>2013-05-22T03:57:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=feaa60662768dcc97fdf7c593583876ce4e1564c'/>
<id>urn:sha1:feaa60662768dcc97fdf7c593583876ce4e1564c</id>
<content type='text'>
Qemu emulates the Galileo GT64120 System Controller
which provides a CPU bus to PCI bus bridge.

The patch adds driver for this bridge and enables
PCI support for the emulated Malta board.

Signed-off-by: Gabor Juhos &lt;juhosg@openwrt.org&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@googlemail.com&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1a4596601fd395f3afb8f82f3f840c5e00bdd57a'/>
<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
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