<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/pci/Makefile, branch v2018.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci/Makefile?h=v2018.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci/Makefile?h=v2018.09'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-05-08T13:07:35Z</updated>
<entry>
<title>pci: intel: Add Intel FPGA PCIe controller driver</title>
<updated>2018-05-08T13:07:35Z</updated>
<author>
<name>Ley Foon Tan</name>
<email>ley.foon.tan@intel.com</email>
</author>
<published>2018-04-20T13:55:45Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7c45862f22fd6275a48130197d315dcf8723cfb5'/>
<id>urn:sha1:7c45862f22fd6275a48130197d315dcf8723cfb5</id>
<content type='text'>
Add PCIe driver for Intel FPGA PCIe IP. This driver operates the PCIe IP in
rootport mode only, the EP mode is not supported. The driver is tested
with the Intel e1000e NIC driver.

Signed-off-by: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=83d290c56fab2d38cd1ab4c4cc7099559c1d5046'/>
<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm64: a37xx: pci: add support for aardvark pcie driver</title>
<updated>2018-03-30T10:52:49Z</updated>
<author>
<name>Wilson Ding</name>
<email>dingwei@marvell.com</email>
</author>
<published>2018-03-26T07:57:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e51f2b14c4936daf3e3040bddb15f63d35e6d988'/>
<id>urn:sha1:e51f2b14c4936daf3e3040bddb15f63d35e6d988</id>
<content type='text'>
This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.

Signed-off-by: Wilson Ding &lt;dingwei@marvell.com&gt;
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725
Reviewed-by: Victor Gu &lt;xigu@marvell.com&gt;
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Tested-by: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>pci: rmobile: Add RCar Gen2 PCIe controller driver</title>
<updated>2018-01-27T19:38:53Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-01-18T13:35:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5f14f7d783f1a3a2e8085738a31b82580addf7b9'/>
<id>urn:sha1:5f14f7d783f1a3a2e8085738a31b82580addf7b9</id>
<content type='text'>
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs.
The PCIe on Gen2 is used both to connect external PCIe peripherals as
well as access the on-SoC USB EHCI controller.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
</content>
</entry>
<entry>
<title>PCI: Drop CONFIG_TSI108_PCI</title>
<updated>2018-01-10T13:05:49Z</updated>
<author>
<name>Tuomas Tynkkynen</name>
<email>tuomas@tuxera.com</email>
</author>
<published>2017-12-18T22:28:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=55acf49eaba0a05d1ca1406d60ec645e992b4641'/>
<id>urn:sha1:55acf49eaba0a05d1ca1406d60ec645e992b4641</id>
<content type='text'>
Last user of this option went away in 2015 in commit:
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")

Signed-off-by: Tuomas Tynkkynen &lt;tuomas@tuxera.com&gt;
</content>
</entry>
<entry>
<title>PCI: Add driver for a 'pci-host-ecam-generic' host controller</title>
<updated>2017-10-06T15:28:12Z</updated>
<author>
<name>Tuomas Tynkkynen</name>
<email>tuomas.tynkkynen@iki.fi</email>
</author>
<published>2017-09-19T20:18:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3675cb044e68bc1145444f3c4f9af5c02864607b'/>
<id>urn:sha1:3675cb044e68bc1145444f3c4f9af5c02864607b</id>
<content type='text'>
QEMU emulates such a device with '-machine virt,highmem=off' on ARM.
The 'highmem=off' part is required for things to work as the PCI code
in U-Boot doesn't seem to support 64-bit BARs.

Signed-off-by: Tuomas Tynkkynen &lt;tuomas.tynkkynen@iki.fi&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Drop CONFIG_WINBOND_83C553</title>
<updated>2017-01-25T22:38:43Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-01-23T20:31:24Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=37b499c43fbf91b65520d7e2bd7bb998c7ba38e2'/>
<id>urn:sha1:37b499c43fbf91b65520d7e2bd7bb998c7ba38e2</id>
<content type='text'>
This is not used in U-Boot. Drop this option and associated dead code.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci: layerscape: move kernel DT fixup to a separate file</title>
<updated>2017-01-18T17:26:24Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2016-12-13T06:54:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a7294aba086fb05ef2bbb50098a84d6c81e38a4b'/>
<id>urn:sha1:a7294aba086fb05ef2bbb50098a84d6c81e38a4b</id>
<content type='text'>
To make the layerscape pcie driver clear, move the kernel DT fixup
code from pcie_layerscape.c to pcie_layerscape_fixup.c.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: mvebu: Add PCIe driver for Armada-8K</title>
<updated>2016-12-05T12:34:33Z</updated>
<author>
<name>Shadi Ammouri</name>
<email>shadi@marvell.com</email>
</author>
<published>2016-10-27T11:29:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=182ba1a7dfe94fed21eff666cc1a4f38c7a3e88e'/>
<id>urn:sha1:182ba1a7dfe94fed21eff666cc1a4f38c7a3e88e</id>
<content type='text'>
This patch adds a driver for the PCIe controller integrated in the
Marvell Armada-8K SoC. This controller is based on the DesignWare
IP core.

The original version was written by Shadi and Yehuda. I ported this
driver to the latest mainline U-Boot version with DM support.

Tested on the Marvell DB-88F8040 Armada-8K eval board.

Signed-off-by: Shadi Ammouri &lt;shadi@marvell.com&gt;
Signed-off-by: Yehuda Yitschak &lt;yehuday@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Neta Zur Hershkovits &lt;neta@marvell.com&gt;
Cc: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Cc: Omri Itach &lt;omrii@marvell.com&gt;
Cc: Igal Liberman &lt;igall@marvell.com&gt;
Cc: Haim Boot &lt;hayim@marvell.com&gt;
Cc: Hanna Hawa &lt;hannah@marvell.com&gt;
</content>
</entry>
<entry>
<title>pci: xilinx: Add a driver for Xilinx AXI to PCIe bridge</title>
<updated>2016-09-21T13:04:32Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2016-09-08T06:47:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a29e45a9c468ba254bbf18886454c53ff16bec49'/>
<id>urn:sha1:a29e45a9c468ba254bbf18886454c53ff16bec49</id>
<content type='text'>
This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
