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<title>u-boot.git/drivers/pci/Makefile, branch v2020.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci/Makefile?h=v2020.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci/Makefile?h=v2020.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2019-12-03T13:43:24Z</updated>
<entry>
<title>pci: Only link pci_rom.o in some cases</title>
<updated>2019-12-03T13:43:24Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-11-27T01:40:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=923e211f8d92d67caa93125f1aff2ae123c6b9d5'/>
<id>urn:sha1:923e211f8d92d67caa93125f1aff2ae123c6b9d5</id>
<content type='text'>
The content of pci_rom.c is only used in a few cases.  Only build and
link in these cases to avoid a global variable as gcc doesn't always
discard those when they are unused.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: add initial support for the Phytium Durian Board</title>
<updated>2019-11-07T23:01:13Z</updated>
<author>
<name>liu hao</name>
<email>steven_hao5189@outlook.com</email>
</author>
<published>2019-10-31T07:51:08Z</published>
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<id>urn:sha1:e3aafef4cf2d16e14e3bc02c3d8dbd434e305c19</id>
<content type='text'>
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Cc: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;

Signed-off-by: Steven Hao &lt;liuhao@phytium.com.cn&gt;
</content>
</entry>
<entry>
<title>pci: add DM based mpc85xx driver</title>
<updated>2019-11-06T11:00:19Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2019-10-14T09:29:39Z</published>
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<id>urn:sha1:b61cbbdcabbd56da83eed401b813766e2ef994dc</id>
<content type='text'>
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.c

In the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: mediatek: add PCIe controller support for MT7623</title>
<updated>2019-10-11T14:09:58Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2019-08-22T10:26:49Z</published>
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<id>urn:sha1:42d37450e50b3a763d95fe1ff46499b9e564596e</id>
<content type='text'>
This adds PCIe controller support for MT7623.
This is adapted from the Linux version.

Tested-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Signed-off-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
</content>
</entry>
<entry>
<title>pcie: ti: add driver for AM65x PCIe RC</title>
<updated>2019-08-12T17:33:39Z</updated>
<author>
<name>Sekhar Nori</name>
<email>nsekhar@ti.com</email>
</author>
<published>2019-08-01T13:42:57Z</published>
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<id>urn:sha1:03c396bb5f3e74c74ce164b9b1eef9908e5cfabb</id>
<content type='text'>
Add driver supporting PCIe root-complex available
on TI's AM65x SoC.

Signed-off-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: add Freescale PowerPC PCIe driver</title>
<updated>2019-06-20T05:14:45Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2019-04-24T14:33:02Z</published>
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<id>urn:sha1:b89e3d9250046c3e7c956fd5e7a14364747433a4</id>
<content type='text'>
Add PCIe DM driver for Freescale PowerPC PCIe controllers.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-sh</title>
<updated>2019-05-27T00:18:20Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-05-27T00:18:20Z</published>
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<id>urn:sha1:c18b103657d9541305a45a1fb21f979c317fba49</id>
<content type='text'>
- Gen3 PCIe driver + enablement on Salvator-X platforms.
- Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon.
- SDHI HS400 fixes ported from latest BSP and datasheet.
</content>
</entry>
<entry>
<title>pci: ls_pcie_g4: add device tree fixups for PCI Stream IDs</title>
<updated>2019-05-22T06:54:24Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2019-04-08T10:15:54Z</published>
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<id>urn:sha1:1d341bc4b6b357e7348ab4393247e369aeb30aa6</id>
<content type='text'>
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs</title>
<updated>2019-05-22T06:54:24Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2019-04-08T10:15:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=07ce19f5e9ad637caa8cb2b6db45a6a28d2d69a1'/>
<id>urn:sha1:07ce19f5e9ad637caa8cb2b6db45a6a28d2d69a1</id>
<content type='text'>
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Signed-off-by: Bao Xiaowei &lt;Xiaowei.Bao@nxp.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: renesas: Add RCar Gen3 PCIe controller driver</title>
<updated>2019-05-21T20:15:31Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-10-16T10:49:19Z</published>
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<id>urn:sha1:776abedef473659f165dd018388e8b5d81a5c54c</id>
<content type='text'>
Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs.
The PCIe on Gen3 is used both to connect external PCIe peripherals.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
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