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<title>u-boot.git/drivers/pci/Makefile, branch v2020.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci/Makefile?h=v2020.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci/Makefile?h=v2020.07'/>
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<updated>2020-05-22T12:53:20Z</updated>
<entry>
<title>pci: Add Rockchip PCIe PHY controller driver</title>
<updated>2020-05-22T12:53:20Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-09T16:56:22Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=89f2fa0b5e82fa5fa05e5bce0e24bc1d863270ce'/>
<id>urn:sha1:89f2fa0b5e82fa5fa05e5bce0e24bc1d863270ce</id>
<content type='text'>
Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.

The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.

Say if we try to get the PCIe PHY then the phy-uclass
will look for PHY in the first instance if it is not
in the root node it will try to probe the parent by
assuming that the actual PHY is inside the parent PHY
of UCLASS_PHY. But, in rk3399 hardware representation
PHY like emmc, usb and pcie are part of syscon which
is completely a different of UCLASS_SYSCON.

Example:

grf: syscon@ff770000 {
   compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
   reg = &lt;0x0 0xff770000 0x0 0x10000&gt;;
   #address-cells = &lt;1&gt;;
   #size-cells = &lt;1&gt;;

   pcie_phy: pcie-phy {
       compatible = "rockchip,rk3399-pcie-phy";
       clocks = &lt;&amp;cru SCLK_PCIEPHY_REF&gt;;
       clock-names = "refclk";
       #phy-cells = &lt;1&gt;;
       resets = &lt;&amp;cru SRST_PCIEPHY&gt;;
       drive-impedance-ohm = &lt;50&gt;;
       reset-names = "phy";
       status = "disabled";
   };
};

Due to this limitation, this patch adds a separate PHY
driver for Rockchip PCIe. This might be removed in future
once Generic PHY supports this limitation.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Suniel Mahesh &lt;sunil@amarulasolutions.com&gt; #roc-rk3399-pc
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>pci: Add Rockchip PCIe controller driver</title>
<updated>2020-05-22T12:53:20Z</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-09T16:56:21Z</published>
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<id>urn:sha1:99d59069c0a18147b1a475236b0632d085315c43</id>
<content type='text'>
Add Rockchip PCIe controller driver for rk3399 platform.

Driver support Gen1 by operating as a Root complex.

Thanks to Patrick for initial work.

Signed-off-by: Patrick Wildt &lt;patrick@blueri.se&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Tested-by: Suniel Mahesh &lt;sunil@amarulasolutions.com&gt; #roc-rk3399-pc
</content>
</entry>
<entry>
<title>pci: layerscape: Common device tree fixup for NXP SoCs</title>
<updated>2020-01-24T08:58:26Z</updated>
<author>
<name>Wasim Khan</name>
<email>wasim.khan@nxp.com</email>
</author>
<published>2020-01-06T12:05:57Z</published>
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<id>urn:sha1:1185b229cca55a5ce3ee7bb35b203f788254f1a1</id>
<content type='text'>
Add Common device tree fixup for NXP SoCs. Based on
SoC and revision call pcie_layerscape or pcie_layerscape_gen4
fixup.

Signed-off-by: Wasim Khan &lt;wasim.khan@nxp.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>drivers/pci : enable pcie_layerscape code for lx2160a rev2</title>
<updated>2019-12-26T10:30:21Z</updated>
<author>
<name>Wasim Khan</name>
<email>wasim.khan@nxp.com</email>
</author>
<published>2019-11-15T09:23:32Z</published>
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<id>urn:sha1:5ff7b84084260f0e28358de6a5129ee0ef6f863d</id>
<content type='text'>
lx2160a rev1 uses pcie_layerscape_gen4 driver and lx2160a rev2 uses
pcie_layerscape driver.
Enable pcie_layerscape code for CONFIG_PCIE_LAYERSCAPE_GEN4.
Based on SoC and revision pcie controller probe will be invoked.

Signed-off-by: Wasim Khan &lt;wasim.khan@nxp.com&gt;
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: Only link pci_rom.o in some cases</title>
<updated>2019-12-03T13:43:24Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-11-27T01:40:59Z</published>
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<id>urn:sha1:923e211f8d92d67caa93125f1aff2ae123c6b9d5</id>
<content type='text'>
The content of pci_rom.c is only used in a few cases.  Only build and
link in these cases to avoid a global variable as gcc doesn't always
discard those when they are unused.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: add initial support for the Phytium Durian Board</title>
<updated>2019-11-07T23:01:13Z</updated>
<author>
<name>liu hao</name>
<email>steven_hao5189@outlook.com</email>
</author>
<published>2019-10-31T07:51:08Z</published>
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<id>urn:sha1:e3aafef4cf2d16e14e3bc02c3d8dbd434e305c19</id>
<content type='text'>
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Cc: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;

Signed-off-by: Steven Hao &lt;liuhao@phytium.com.cn&gt;
</content>
</entry>
<entry>
<title>pci: add DM based mpc85xx driver</title>
<updated>2019-11-06T11:00:19Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2019-10-14T09:29:39Z</published>
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<id>urn:sha1:b61cbbdcabbd56da83eed401b813766e2ef994dc</id>
<content type='text'>
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.c

In the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: mediatek: add PCIe controller support for MT7623</title>
<updated>2019-10-11T14:09:58Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2019-08-22T10:26:49Z</published>
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<id>urn:sha1:42d37450e50b3a763d95fe1ff46499b9e564596e</id>
<content type='text'>
This adds PCIe controller support for MT7623.
This is adapted from the Linux version.

Tested-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Signed-off-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
</content>
</entry>
<entry>
<title>pcie: ti: add driver for AM65x PCIe RC</title>
<updated>2019-08-12T17:33:39Z</updated>
<author>
<name>Sekhar Nori</name>
<email>nsekhar@ti.com</email>
</author>
<published>2019-08-01T13:42:57Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=03c396bb5f3e74c74ce164b9b1eef9908e5cfabb'/>
<id>urn:sha1:03c396bb5f3e74c74ce164b9b1eef9908e5cfabb</id>
<content type='text'>
Add driver supporting PCIe root-complex available
on TI's AM65x SoC.

Signed-off-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: add Freescale PowerPC PCIe driver</title>
<updated>2019-06-20T05:14:45Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2019-04-24T14:33:02Z</published>
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<id>urn:sha1:b89e3d9250046c3e7c956fd5e7a14364747433a4</id>
<content type='text'>
Add PCIe DM driver for Freescale PowerPC PCIe controllers.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
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