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<title>u-boot.git/drivers/pci/pci-uclass.c, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci/pci-uclass.c?h=main</id>
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<updated>2026-06-25T00:13:24Z</updated>
<entry>
<title>treewide: move bi_dram[] from bd to gd</title>
<updated>2026-06-25T00:13:24Z</updated>
<author>
<name>Ilias Apalodimas</name>
<email>ilias.apalodimas@linaro.org</email>
</author>
<published>2026-06-17T07:48:19Z</published>
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<id>urn:sha1:1174c99ab421168221be372bd83a4143bf5f167d</id>
<content type='text'>
Currently, the bi_dram[] information is stored in the board info
structure (bd). Because bd is only valid after reserve_board(),
dram_init_banksize() must be called late in the initialization process.
This limitation is problematic, as it forces us to rely on a variety of
bespoke functions to determine board RAM, bank memory sizes, and other
early setup requirements.

By moving bi_dram[] into the global data (gd), we can run it earlier.
This is particularly convenient since boards define their own
dram_init_banksize() routines, which do not always rely on parsing
Device Tree (DT) memory nodes.

Additionally, U-Boot defaults to relocating to the top of the first memory
bank. While boards currently use custom functions to override this
behavior, having the DRAM bank information available earlier in gd makes
relocating to a different bank trivial and standardizes the process.

Reviewed-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Tested-by: Michal Simek &lt;michal.simek@amd.com&gt; # Versal Gen 2 Vek385
Tested-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Tested-by: Christophe Leroy (CS GROUP) &lt;chleroy@kernel.org&gt;
</content>
</entry>
<entry>
<title>pci: correct PCI device enumeration to include all functions on device 0</title>
<updated>2026-04-27T17:11:08Z</updated>
<author>
<name>Maximilian Brune</name>
<email>maximilian.brune@9elements.com</email>
</author>
<published>2026-04-22T12:57:53Z</published>
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<id>urn:sha1:6ab5b5d2804b00d3253d09c6d8f829d918d2ed1c</id>
<content type='text'>
Currently the implementation does not just skip all devices beside
device 0, it also skips all functions (besides 0) on device 0. This
broke basically all AMD platforms, since they have a lot of internal SOC
devices behind these functions.

This was detected, because the XHCI controller and therefore the USB
devices were not found by u-boot on AMD/crater platform.

PCI_MASK_BUS() returns both device and function bits, so it skips any
bdf where either device &gt; 0 or function &gt; 0. Using PCI_DEV() extracts
only the device number, matching the intent in only_one_child().
It therefore now checks all functions on device 0 (Linux does the same).

I build tested u-boot as coreboot payload and run it on a recent x86 AMD
platform. Devices like the XHCI controller are now found again.

Fixes: fbde868ba4aa ("pci: skip unnecessary PCIe scanning")
Signed-off-by: Maximilian Brune &lt;maximilian.brune@9elements.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
CC: Tom Rini &lt;trini@konsulko.com&gt;
CC: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
CC: George McCollister &lt;george.mccollister@konsulko.com&gt;
CC: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci: skip unnecessary PCIe scanning</title>
<updated>2026-02-04T16:40:28Z</updated>
<author>
<name>George McCollister</name>
<email>george.mccollister@konsulko.com</email>
</author>
<published>2026-01-30T15:38:01Z</published>
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<id>urn:sha1:fbde868ba4aa05d6f04d4969a63e86607f725f59</id>
<content type='text'>
Use the same mechanism as the Linux kernel to skip unnecessary (and in
the case of the J722S, errant) scanning of direct children of root
ports, downstream ports or bridges.

Based on Linux PCI code in the following files as of b927546677c8:
  drivers/pci/probe.c
  drivers/pci/pci.h
  include/linux/pci.h

Signed-off-by: George McCollister &lt;george.mccollister@konsulko.com&gt;
Tested-by: Bryan Brattlof &lt;bb@ti.com&gt;
</content>
</entry>
<entry>
<title>pci: Assign a default value on reads on error</title>
<updated>2025-07-14T21:16:48Z</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2025-07-07T16:26:53Z</published>
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<id>urn:sha1:22039ef94a8f6e7f4fc04648dc5a0ee857927be3</id>
<content type='text'>
Many callers of PCI read functions do not check the return value for
error before using the variable that should contain the value read were
there not to be an error. However in the error case this variable is
never assigned to and so will contain uninitialised data.
To provide some certainty as to behaviour in the error case assign a
default value of all bits set.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
</content>
</entry>
<entry>
<title>xpl: Rename spl_phase() to xpl_phase()</title>
<updated>2024-10-11T17:44:47Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-09-30T01:49:36Z</published>
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<id>urn:sha1:456bdb70def1fe371f964e82158a53f6baf1d3a4</id>
<content type='text'>
Rename this function to indicate that it refers to any xPL phase.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"</title>
<updated>2024-05-20T19:35:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-20T19:35:03Z</published>
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<id>urn:sha1:03de305ec48b0bb28554372abb40ccd46dbe0bf9</id>
<content type='text'>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43Z</published>
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<id>urn:sha1:d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>pci: Remove &lt;common.h&gt; and add needed includes</title>
<updated>2024-05-07T14:00:55Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-02T01:31:05Z</published>
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<id>urn:sha1:8db017c891420fe161e478feb63460e41ef0a5d5</id>
<content type='text'>
Remove &lt;common.h&gt; from this driver directory and when needed
add missing include files directly.

Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>drivers: pci: Fix dm_pci_map_bar() to support 64b BARs</title>
<updated>2024-01-19T01:24:13Z</updated>
<author>
<name>Moritz Fischer</name>
<email>moritzf@google.com</email>
</author>
<published>2024-01-10T04:59:02Z</published>
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<id>urn:sha1:040834703497bafb81fce88a92d8e54c8837fcaa</id>
<content type='text'>
This enables 64b BARs if CONFIG_SYS_PCI_64BIT is enabled.

Reviewed-by: Philip Oberfichtner &lt;pro@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Moritz Fischer &lt;moritzf@google.com&gt;
</content>
</entry>
<entry>
<title>pci: serial: Support reading PCI-register size with base</title>
<updated>2023-10-06T18:38:13Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-09-26T14:14:58Z</published>
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<id>urn:sha1:f69d3d6d10b15872a279aeb10b7c522627aff6c2</id>
<content type='text'>
The PCI helpers read only the base address for a PCI region. In some cases
the size is needed as well, e.g. to pass along to a driver which needs to
know the size of its register area.

Update the functions to allow the size to be returned. For serial, record
the information and provided it with the serial_info() call.

A limitation still exists in that the size is not available when OF_LIVE
is enabled, so take account of that in the tests.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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