u-boot.git/drivers/pci, branch master

pci: correct PCI device enumeration to include all functions on device 0

2026-04-27T17:11:08+00:00

Currently the implementation does not just skip all devices beside
device 0, it also skips all functions (besides 0) on device 0. This
broke basically all AMD platforms, since they have a lot of internal SOC
devices behind these functions.

This was detected, because the XHCI controller and therefore the USB
devices were not found by u-boot on AMD/crater platform.

PCI_MASK_BUS() returns both device and function bits, so it skips any
bdf where either device > 0 or function > 0. Using PCI_DEV() extracts
only the device number, matching the intent in only_one_child().
It therefore now checks all functions on device 0 (Linux does the same).

I build tested u-boot as coreboot payload and run it on a recent x86 AMD
platform. Devices like the XHCI controller are now found again.

Fixes: fbde868ba4aa ("pci: skip unnecessary PCIe scanning")
Signed-off-by: Maximilian Brune 
Reviewed-by: Simon Glass 
CC: Tom Rini 
CC: Andrew Goodbody 
CC: George McCollister 
CC: Simon Glass

pci: Add AMD Versal2 DW PCIe host controller driver

2026-04-23T09:49:48+00:00

Add support for the DesignWare-based PCIe host controller found in
AMD Versal2 SoCs. This enables PCIe functionality (e.g. NVMe storage)
on boards such as the VEK385.

The driver builds on the existing pcie_dw_common infrastructure and
adds Versal2-specific handling: it maps the SLCR register region to
mask and clear TLP interrupt status bits, parses dbi/config/atu/slcr
register regions from device tree, and supports an optional PERST#
GPIO on child nodes for endpoint reset sequencing. The outbound iATU
is programmed for the non-prefetchable memory window from device tree
ranges.

Signed-off-by: Pranav Sanwal 
Link: https://lore.kernel.org/r/20260327121015.996806-2-pranav.sanwal@amd.com
Signed-off-by: Michal Simek

pci: imx: Properly support upstream Linux reset-gpios property

2026-04-02T12:05:06+00:00

The driver requests explicitly "reset-gpio" property, not the one with
"gpios" suffix but upstream Linux kernel deprecated it in 2021.
Existing upstream Linux kernel DTS is being changed to "reset-gpios"
property, thus update the driver to read that one too.

Note that driver is probably broken already, because it parsed GPIO in
standard way respecting the flags and on top of that applied the
"reset-gpio-active-high" flag, thus "reset-gpio ACTIVE_LOW" with the
"reset-gpio-active-high" property would be double inverted.

Signed-off-by: Krzysztof Kozlowski

pcie: starfive: Add a optional power gpio support

2026-03-16T17:36:57+00:00

Get and enable a optional power gpio. This feature is ported
from the jh7110 pcie driver in Linux. VisionFive 2 Lite needs
this gpio to enable the PCI bus device (M.2 M-Key) power.

Signed-off-by: Hal Feng

Merge tag 'v2026.04-rc4' into next

2026-03-09T21:26:34+00:00

Prepare v2026.04-rc4

pci: pcie_cdns_ti: enable PCIe root-complex mode for J784S4 SoC

2026-03-09T15:35:43+00:00

The PCIe Controllers on the J784S4 SoC support Root-Complex mode of
operation. Hence, enable it.

Signed-off-by: Siddharth Vadapalli 
Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")

treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage

2026-02-17T19:50:22+00:00

Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.

Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.

Reviewed-by: Patrice Chotard  #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal  #TI boards
Acked-by: Yao Zi  #TH1520
Signed-off-by: Peng Fan

pci: layerspace: Add missing header files

2026-02-17T19:50:22+00:00

struct fdt_resource, u32 and bool types are used in this header, add
missing header files following "include what you use".

Signed-off-by: Peng Fan

Merge patch series "arm: k3: j722s: add PCIe support"

2026-02-04T16:40:37+00:00

George McCollister  says:

This patch series brings over several changes from Linux that are required
to get PCIe working on the j722s and also enables PCIe in
j722s_evm_a53_defconfig. This allows Linux to be booted from an NVMe drive.

The J722S SoC provides pcie0 (using pcie_cdns_ti) thru serdes1
(using phy-cadence-torrent) thru serdes_wiz1 (using phy-j721e-wiz). Changes
to the three drivers needed to be ported from Linux to enable the REFCLK
output which is used with this SoC. These changes should be tested on other
platforms using these drivers by those with the hardware available to make
sure no problems were introduced.

The PCIe controller in this SoC relies on the code performing the PCI scan
not scanning devices which cannot exist. In Linux this is implemented as
only_one_child() in probe.c. If this mechanism is not used, PCI config reads
for subsequent functions will return information for device 0 resulting in
U-Boot detecting 32 devices when only 1 is present. This change should be
tested on other platforms with PCI to ensure the same PCI devices are
enumerated before and after the patch is applied.

I would like to thank Opto 22 for sponsoring the initial development and
anyone that is able to contribute to testing of patches.

Link: https://lore.kernel.org/r/20260130153856.2049575-1-george.mccollister@konsulko.com

pci: pcie_cdns_ti: Add PCIe support for J722S SoC

2026-02-04T16:40:28+00:00

TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3
single lane PCIe controller. Add support for the "ti,j722s-pcie-host"
compatible specific to J722S SoC.

Based on:
https://lore.kernel.org/all/20240524092349.158443-1-s-vadapalli@ti.com/

Signed-off-by: George McCollister 
Tested-by: Bryan Brattlof