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<title>u-boot.git/drivers/pci, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>pci: imx: Properly support upstream Linux reset-gpios property</title>
<updated>2026-04-02T12:05:06+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@oss.qualcomm.com</email>
</author>
<published>2026-03-12T19:26:05+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=97979e894ba14d67e926322f4f770e3591a3e53c'/>
<id>97979e894ba14d67e926322f4f770e3591a3e53c</id>
<content type='text'>
The driver requests explicitly "reset-gpio" property, not the one with
"gpios" suffix but upstream Linux kernel deprecated it in 2021.
Existing upstream Linux kernel DTS is being changed to "reset-gpios"
property, thus update the driver to read that one too.

Note that driver is probably broken already, because it parsed GPIO in
standard way respecting the flags and on top of that applied the
"reset-gpio-active-high" flag, thus "reset-gpio ACTIVE_LOW" with the
"reset-gpio-active-high" property would be double inverted.

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@oss.qualcomm.com&gt;
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<pre>
The driver requests explicitly "reset-gpio" property, not the one with
"gpios" suffix but upstream Linux kernel deprecated it in 2021.
Existing upstream Linux kernel DTS is being changed to "reset-gpios"
property, thus update the driver to read that one too.

Note that driver is probably broken already, because it parsed GPIO in
standard way respecting the flags and on top of that applied the
"reset-gpio-active-high" flag, thus "reset-gpio ACTIVE_LOW" with the
"reset-gpio-active-high" property would be double inverted.

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@oss.qualcomm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pcie: starfive: Add a optional power gpio support</title>
<updated>2026-03-16T17:36:57+00:00</updated>
<author>
<name>Hal Feng</name>
<email>hal.feng@starfivetech.com</email>
</author>
<published>2025-10-24T08:59:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a10587939bcc7d9325dbe24cde335a65887f9377'/>
<id>a10587939bcc7d9325dbe24cde335a65887f9377</id>
<content type='text'>
Get and enable a optional power gpio. This feature is ported
from the jh7110 pcie driver in Linux. VisionFive 2 Lite needs
this gpio to enable the PCI bus device (M.2 M-Key) power.

Signed-off-by: Hal Feng &lt;hal.feng@starfivetech.com&gt;
</content>
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<pre>
Get and enable a optional power gpio. This feature is ported
from the jh7110 pcie driver in Linux. VisionFive 2 Lite needs
this gpio to enable the PCI bus device (M.2 M-Key) power.

Signed-off-by: Hal Feng &lt;hal.feng@starfivetech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'v2026.04-rc4' into next</title>
<updated>2026-03-09T21:26:34+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-03-09T21:26:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1e240f7206fccde4ec73ea432ab8360d321c5fe5'/>
<id>1e240f7206fccde4ec73ea432ab8360d321c5fe5</id>
<content type='text'>
Prepare v2026.04-rc4
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<pre>
Prepare v2026.04-rc4
</pre>
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</content>
</entry>
<entry>
<title>pci: pcie_cdns_ti: enable PCIe root-complex mode for J784S4 SoC</title>
<updated>2026-03-09T15:35:43+00:00</updated>
<author>
<name>Siddharth Vadapalli</name>
<email>s-vadapalli@ti.com</email>
</author>
<published>2026-02-27T11:58:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=068d05ad5f82a58316e895fd1497cf10898b3beb'/>
<id>068d05ad5f82a58316e895fd1497cf10898b3beb</id>
<content type='text'>
The PCIe Controllers on the J784S4 SoC support Root-Complex mode of
operation. Hence, enable it.

Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
</content>
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<pre>
The PCIe Controllers on the J784S4 SoC support Root-Complex mode of
operation. Hence, enable it.

Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
Fixes: 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
</pre>
</div>
</content>
</entry>
<entry>
<title>treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage</title>
<updated>2026-02-17T19:50:22+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2026-02-09T01:30:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0f90b1e715f8abe41b0875752eb184f46032ff11'/>
<id>0f90b1e715f8abe41b0875752eb184f46032ff11</id>
<content type='text'>
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.

Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.

Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt; #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal &lt;anshuld@ti.com&gt; #TI boards
Acked-by: Yao Zi &lt;me@ziyao.cc&gt; #TH1520
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
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<pre>
Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and
drop the unnecessary inclusion of asm/global_data.h.

Headers should be included directly by the files that need them,
rather than indirectly via global_data.h.

Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt; #STMicroelectronics boards and STM32MP1 ram test driver
Tested-by: Anshul Dalal &lt;anshuld@ti.com&gt; #TI boards
Acked-by: Yao Zi &lt;me@ziyao.cc&gt; #TH1520
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: layerspace: Add missing header files</title>
<updated>2026-02-17T19:50:22+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2026-02-09T01:30:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d3b0b3c1184744a3471ca98363b7bc31e7ccb882'/>
<id>d3b0b3c1184744a3471ca98363b7bc31e7ccb882</id>
<content type='text'>
struct fdt_resource, u32 and bool types are used in this header, add
missing header files following "include what you use".

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
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<pre>
struct fdt_resource, u32 and bool types are used in this header, add
missing header files following "include what you use".

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge patch series "arm: k3: j722s: add PCIe support"</title>
<updated>2026-02-04T16:40:37+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-02-04T16:40:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5f0b0ad72246382cadcd469ef6724961c7720b0e'/>
<id>5f0b0ad72246382cadcd469ef6724961c7720b0e</id>
<content type='text'>
George McCollister &lt;george.mccollister@konsulko.com&gt; says:

This patch series brings over several changes from Linux that are required
to get PCIe working on the j722s and also enables PCIe in
j722s_evm_a53_defconfig. This allows Linux to be booted from an NVMe drive.

The J722S SoC provides pcie0 (using pcie_cdns_ti) thru serdes1
(using phy-cadence-torrent) thru serdes_wiz1 (using phy-j721e-wiz). Changes
to the three drivers needed to be ported from Linux to enable the REFCLK
output which is used with this SoC. These changes should be tested on other
platforms using these drivers by those with the hardware available to make
sure no problems were introduced.

The PCIe controller in this SoC relies on the code performing the PCI scan
not scanning devices which cannot exist. In Linux this is implemented as
only_one_child() in probe.c. If this mechanism is not used, PCI config reads
for subsequent functions will return information for device 0 resulting in
U-Boot detecting 32 devices when only 1 is present. This change should be
tested on other platforms with PCI to ensure the same PCI devices are
enumerated before and after the patch is applied.

I would like to thank Opto 22 for sponsoring the initial development and
anyone that is able to contribute to testing of patches.

Link: https://lore.kernel.org/r/20260130153856.2049575-1-george.mccollister@konsulko.com
</content>
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<pre>
George McCollister &lt;george.mccollister@konsulko.com&gt; says:

This patch series brings over several changes from Linux that are required
to get PCIe working on the j722s and also enables PCIe in
j722s_evm_a53_defconfig. This allows Linux to be booted from an NVMe drive.

The J722S SoC provides pcie0 (using pcie_cdns_ti) thru serdes1
(using phy-cadence-torrent) thru serdes_wiz1 (using phy-j721e-wiz). Changes
to the three drivers needed to be ported from Linux to enable the REFCLK
output which is used with this SoC. These changes should be tested on other
platforms using these drivers by those with the hardware available to make
sure no problems were introduced.

The PCIe controller in this SoC relies on the code performing the PCI scan
not scanning devices which cannot exist. In Linux this is implemented as
only_one_child() in probe.c. If this mechanism is not used, PCI config reads
for subsequent functions will return information for device 0 resulting in
U-Boot detecting 32 devices when only 1 is present. This change should be
tested on other platforms with PCI to ensure the same PCI devices are
enumerated before and after the patch is applied.

I would like to thank Opto 22 for sponsoring the initial development and
anyone that is able to contribute to testing of patches.

Link: https://lore.kernel.org/r/20260130153856.2049575-1-george.mccollister@konsulko.com
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: pcie_cdns_ti: Add PCIe support for J722S SoC</title>
<updated>2026-02-04T16:40:28+00:00</updated>
<author>
<name>George McCollister</name>
<email>george.mccollister@konsulko.com</email>
</author>
<published>2026-01-30T15:38:05+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=795b1fd2dff8a8abc464c9f9a85e0b11966bbd1b'/>
<id>795b1fd2dff8a8abc464c9f9a85e0b11966bbd1b</id>
<content type='text'>
TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3
single lane PCIe controller. Add support for the "ti,j722s-pcie-host"
compatible specific to J722S SoC.

Based on:
https://lore.kernel.org/all/20240524092349.158443-1-s-vadapalli@ti.com/

Signed-off-by: George McCollister &lt;george.mccollister@konsulko.com&gt;
Tested-by: Bryan Brattlof &lt;bb@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
TI's J722S SoC has one instance of PCIe namely PCIe0 which is a Gen3
single lane PCIe controller. Add support for the "ti,j722s-pcie-host"
compatible specific to J722S SoC.

Based on:
https://lore.kernel.org/all/20240524092349.158443-1-s-vadapalli@ti.com/

Signed-off-by: George McCollister &lt;george.mccollister@konsulko.com&gt;
Tested-by: Bryan Brattlof &lt;bb@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: pcie_cdns_ti: Add support to provide refclk to PCIe connector</title>
<updated>2026-02-04T16:40:28+00:00</updated>
<author>
<name>George McCollister</name>
<email>george.mccollister@konsulko.com</email>
</author>
<published>2026-01-30T15:38:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3d07fe1390b352b897683f3eaf7ee62786474144'/>
<id>3d07fe1390b352b897683f3eaf7ee62786474144</id>
<content type='text'>
Add support to provide refclk to PCIe connector.

Based on: https://lore.kernel.org/r/20210308063550.6227-5-kishon@ti.com

Signed-off-by: George McCollister &lt;george.mccollister@konsulko.com&gt;
Tested-by: Bryan Brattlof &lt;bb@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support to provide refclk to PCIe connector.

Based on: https://lore.kernel.org/r/20210308063550.6227-5-kishon@ti.com

Signed-off-by: George McCollister &lt;george.mccollister@konsulko.com&gt;
Tested-by: Bryan Brattlof &lt;bb@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: skip unnecessary PCIe scanning</title>
<updated>2026-02-04T16:40:28+00:00</updated>
<author>
<name>George McCollister</name>
<email>george.mccollister@konsulko.com</email>
</author>
<published>2026-01-30T15:38:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fbde868ba4aa05d6f04d4969a63e86607f725f59'/>
<id>fbde868ba4aa05d6f04d4969a63e86607f725f59</id>
<content type='text'>
Use the same mechanism as the Linux kernel to skip unnecessary (and in
the case of the J722S, errant) scanning of direct children of root
ports, downstream ports or bridges.

Based on Linux PCI code in the following files as of b927546677c8:
  drivers/pci/probe.c
  drivers/pci/pci.h
  include/linux/pci.h

Signed-off-by: George McCollister &lt;george.mccollister@konsulko.com&gt;
Tested-by: Bryan Brattlof &lt;bb@ti.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use the same mechanism as the Linux kernel to skip unnecessary (and in
the case of the J722S, errant) scanning of direct children of root
ports, downstream ports or bridges.

Based on Linux PCI code in the following files as of b927546677c8:
  drivers/pci/probe.c
  drivers/pci/pci.h
  include/linux/pci.h

Signed-off-by: George McCollister &lt;george.mccollister@konsulko.com&gt;
Tested-by: Bryan Brattlof &lt;bb@ti.com&gt;
</pre>
</div>
</content>
</entry>
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