<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/pci, branch v2012.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx</title>
<updated>2012-09-25T19:23:55+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2012-09-25T19:23:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5675b509165b67465a20e5cf71e07f40b449ef0c'/>
<id>5675b509165b67465a20e5cf71e07f40b449ef0c</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: fix some warnings related to assumptions about</title>
<updated>2012-09-21T22:24:34+00:00</updated>
<author>
<name>Kumar Gala</name>
<email>galak@kernel.crashing.org</email>
</author>
<published>2012-09-19T04:47:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cf5787f2a4f1af71e72f4faaee32685c8f82a3dd'/>
<id>cf5787f2a4f1af71e72f4faaee32685c8f82a3dd</id>
<content type='text'>
The following commit introduced some warnings associated with using
pci_addr_t instead of a proper 32-bit data type.

commit af778c6d9e2b945ee03cbc53bb976238a3374f33
Author: Andrew Sharp &lt;andywyse6@gmail.com&gt;
Date:   Wed Aug 1 12:27:16 2012 +0000

    pci: fix errant data types and corresponding access functions

On some platforms pci_addr_t is defined as a 64-bit data type so its not
proper to use with pci_{read,write}_config_dword.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The following commit introduced some warnings associated with using
pci_addr_t instead of a proper 32-bit data type.

commit af778c6d9e2b945ee03cbc53bb976238a3374f33
Author: Andrew Sharp &lt;andywyse6@gmail.com&gt;
Date:   Wed Aug 1 12:27:16 2012 +0000

    pci: fix errant data types and corresponding access functions

On some platforms pci_addr_t is defined as a 64-bit data type so its not
proper to use with pci_{read,write}_config_dword.

Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done</title>
<updated>2012-09-02T12:19:05+00:00</updated>
<author>
<name>Andrew Sharp</name>
<email>andywyse6@gmail.com</email>
</author>
<published>2012-08-29T14:16:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=69fd2d3b0559f221a45e9a86b8ead16490f4e47b'/>
<id>69fd2d3b0559f221a45e9a86b8ead16490f4e47b</id>
<content type='text'>
Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a
quick enumberation of the PCI devices, but don't need any setup work done.
This is very beneficial on platforms that have u-boot loaded by another
boot loader which does a more sophisticated job of setup of PCI devices
than u-boot.  That way, u-boot can just read what's there and get on
with life.  This is what SeaBIOS does.

Signed-off-by: Andrew Sharp &lt;andywyse6@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a
quick enumberation of the PCI devices, but don't need any setup work done.
This is very beneficial on platforms that have u-boot loaded by another
boot loader which does a more sophisticated job of setup of PCI devices
than u-boot.  That way, u-boot can just read what's there and get on
with life.  This is what SeaBIOS does.

Signed-off-by: Andrew Sharp &lt;andywyse6@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: minor cleanup of CONFIG_PCI_PNP usage</title>
<updated>2012-09-02T12:18:19+00:00</updated>
<author>
<name>Andrew Sharp</name>
<email>andywyse6@gmail.com</email>
</author>
<published>2012-08-29T14:16:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=03992ac2c974ae3e169219ba0ccdd94a8ce0146a'/>
<id>03992ac2c974ae3e169219ba0ccdd94a8ce0146a</id>
<content type='text'>
Refactor the common PCI code just a tiny bit surrounding the PCI_PNP
(pciauto) stuff.  Makes the code a tiny bit easier to read, and also
makes it more obvious that almost no platform needs to setup or use the
pci_config_table stuff.

Signed-off-by: Andrew Sharp &lt;andywyse6@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Refactor the common PCI code just a tiny bit surrounding the PCI_PNP
(pciauto) stuff.  Makes the code a tiny bit easier to read, and also
makes it more obvious that almost no platform needs to setup or use the
pci_config_table stuff.

Signed-off-by: Andrew Sharp &lt;andywyse6@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: clean up some whitespace and formatting</title>
<updated>2012-09-02T12:17:52+00:00</updated>
<author>
<name>Andrew Sharp</name>
<email>andywyse6@gmail.com</email>
</author>
<published>2012-08-29T14:16:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cb2bf931dcca9ed0ee514680ed99d51b45036aa9'/>
<id>cb2bf931dcca9ed0ee514680ed99d51b45036aa9</id>
<content type='text'>
I tried to clean up the white space and formatting offenses and
inconsistencies in the generic PCI code that obviously has been around for
some time.  Emphasis on large increases in readability and maintainability
and consistency.  I omitted the platform/processor specific files in
the drivers/pci directory because I wanted to leave those file to those
that care more about them.

Signed-off-by: Andrew Sharp &lt;andywyse6@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
I tried to clean up the white space and formatting offenses and
inconsistencies in the generic PCI code that obviously has been around for
some time.  Emphasis on large increases in readability and maintainability
and consistency.  I omitted the platform/processor specific files in
the drivers/pci directory because I wanted to leave those file to those
that care more about them.

Signed-off-by: Andrew Sharp &lt;andywyse6@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: fix errant data types and corresponding access functions</title>
<updated>2012-09-02T12:17:42+00:00</updated>
<author>
<name>Andrew Sharp</name>
<email>andywyse6@gmail.com</email>
</author>
<published>2012-08-01T12:27:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=af778c6d9e2b945ee03cbc53bb976238a3374f33'/>
<id>af778c6d9e2b945ee03cbc53bb976238a3374f33</id>
<content type='text'>
In a couple of places, unsigned int and pci_config_*_dword were being
used when u16 and _word should be used.  Unsigned int was also being
used in a couple of places that should be pci_addr_t.

Signed-off-by: Andrew Sharp &lt;andywyse6@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In a couple of places, unsigned int and pci_config_*_dword were being
used when u16 and _word should be used.  Unsigned int was also being
used in a couple of places that should be pci_addr_t.

Signed-off-by: Andrew Sharp &lt;andywyse6@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/corenet_ds: Master module for boot from PCIE</title>
<updated>2012-08-23T15:24:15+00:00</updated>
<author>
<name>Liu Gang</name>
<email>Gang.Liu@freescale.com</email>
</author>
<published>2012-08-09T05:10:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b5f7c8732ad99b0c1a7fa456f706de1ab7d74eef'/>
<id>b5f7c8732ad99b0c1a7fa456f706de1ab7d74eef</id>
<content type='text'>
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.

The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.

When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Environment and requirement:

master:
    1. NOR flash for its own u-boot image, ucode and ENV space.
    2. Slave's u-boot image is in master NOR flash.
    3. Normally boot from local NOR flash.
    4. Configure PCIE system if needed.
slave:
    1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
    2. Boot location should be set to one PCIE interface by RCW.
    3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the master module, need to finish these processes:
    1. Initialize the PCIE port and address space.
    2. Set inbound PCIE windows covered slave's u-boot image stored in
       master's NOR flash.
	3. Set outbound windows in order to configure slave's registers
	   for the core's releasing.
    4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
	   or "PCIE3" using the following command:

			setenv bootmaster PCIE1
			saveenv

Signed-off-by: Liu Gang &lt;Gang.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.

The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.

When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Environment and requirement:

master:
    1. NOR flash for its own u-boot image, ucode and ENV space.
    2. Slave's u-boot image is in master NOR flash.
    3. Normally boot from local NOR flash.
    4. Configure PCIE system if needed.
slave:
    1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
    2. Boot location should be set to one PCIE interface by RCW.
    3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the master module, need to finish these processes:
    1. Initialize the PCIE port and address space.
    2. Set inbound PCIE windows covered slave's u-boot image stored in
       master's NOR flash.
	3. Set outbound windows in order to configure slave's registers
	   for the core's releasing.
    4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
	   or "PCIE3" using the following command:

			setenv bootmaster PCIE1
			saveenv

Signed-off-by: Liu Gang &lt;Gang.Liu@freescale.com&gt;
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: declare pciauto functions in header</title>
<updated>2012-03-30T20:46:00+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2012-03-25T12:13:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a3a707257f4666b4bc2e3f4ddd9510f2b9f64aed'/>
<id>a3a707257f4666b4bc2e3f4ddd9510f2b9f64aed</id>
<content type='text'>
The FSL PCI driver uses local prototypes for
pciauto_[pre|post]scan_setup_bridge(), this does not seem right,
so move them to the &lt;pci.h&gt; file.

Fixed a small extern declaration too, this is harmless but distracts
the view since all other prototypes are explicitly external.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The FSL PCI driver uses local prototypes for
pciauto_[pre|post]scan_setup_bridge(), this does not seem right,
so move them to the &lt;pci.h&gt; file.

Fixed a small extern declaration too, this is harmless but distracts
the view since all other prototypes are explicitly external.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: move pciauto_config_init() to pci.h</title>
<updated>2012-03-04T20:13:33+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2012-03-03T10:05:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a1e47b66d98f5caf19895965cfe38c176bbf01e8'/>
<id>a1e47b66d98f5caf19895965cfe38c176bbf01e8</id>
<content type='text'>
Fixing build regressions for the Integrator I get find that a few
boards try to work around the missing declaration of
pciauto_config_init() by declaring it in the local scope. This
does not make sense when the sibling functions are in &lt;pci.h&gt;
so move the function to the header, ridding the build error
in the Integrator and getting rid of the local declarations
here and there.

Reported-by:  Wolfgang Denk &lt;wd@denx.de&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fixing build regressions for the Integrator I get find that a few
boards try to work around the missing declaration of
pciauto_config_init() by declaring it in the local scope. This
does not make sense when the sibling functions are in &lt;pci.h&gt;
so move the function to the header, ridding the build error
in the Integrator and getting rid of the local declarations
here and there.

Reported-by:  Wolfgang Denk &lt;wd@denx.de&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci_ftpci100: Implementation FTPCI100 PCI driver</title>
<updated>2011-12-05T22:13:48+00:00</updated>
<author>
<name>Gavin Guo</name>
<email>gavinguo@andestech.com</email>
</author>
<published>2011-11-28T20:48:14+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=014e46782b6f986766cdaea99b954ae877be4ea5'/>
<id>014e46782b6f986766cdaea99b954ae877be4ea5</id>
<content type='text'>
FTPCI100 is a SoC PCI componenet of Faraday company.
Which is usually built into SoC chips for providing
embedded PCI functions.

Signed-off-by: Gavin Guo &lt;gavinguo@andestech.com&gt;
Signed-off-by: Macpaul Lin &lt;macpaul@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
FTPCI100 is a SoC PCI componenet of Faraday company.
Which is usually built into SoC chips for providing
embedded PCI functions.

Signed-off-by: Gavin Guo &lt;gavinguo@andestech.com&gt;
Signed-off-by: Macpaul Lin &lt;macpaul@andestech.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
