<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/pci, branch v2014.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>kconfig: add blank Kconfig files</title>
<updated>2014-09-24T22:30:28+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-09-16T07:32:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ed36323f6d217050f82a2200475959b8557a47e4'/>
<id>ed36323f6d217050f82a2200475959b8557a47e4</id>
<content type='text'>
This would be useful to start moving various config options.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This would be useful to start moving various config options.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pcie_imx: Add mx6solox support</title>
<updated>2014-09-09T15:24:49+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2014-08-25T17:26:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1b8ad74a6f8cea55a727dc4b399baac46d0daef1'/>
<id>1b8ad74a6f8cea55a727dc4b399baac46d0daef1</id>
<content type='text'>
Let PCI on mx6solox also be supported.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Let PCI on mx6solox also be supported.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: add support for board_pci_fixup_dev function</title>
<updated>2014-09-09T14:15:02+00:00</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2014-08-08T05:49:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0991866cf7a10d4868aa2a10940b4def0f68cc50'/>
<id>0991866cf7a10d4868aa2a10940b4def0f68cc50</id>
<content type='text'>
Some board-level drivers may wish to have per-device fixup functions
for PCI devices.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Some board-level drivers may wish to have per-device fixup functions
for PCI devices.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-imx</title>
<updated>2014-08-29T15:06:51+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-08-29T15:06:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5a1095a830299aef8dd32495e505e92ab1749e89'/>
<id>5a1095a830299aef8dd32495e505e92ab1749e89</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: mx6: fix occasional link failures</title>
<updated>2014-08-20T10:37:15+00:00</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2014-08-08T05:57:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5a82e1a21d1229e7e3d1c64187735794019e9a1b'/>
<id>5a82e1a21d1229e7e3d1c64187735794019e9a1b</id>
<content type='text'>
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.

Without this patch we find a high link failure rate (&gt;5%) on certain
IMX6 boards at various temperatures.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.

Without this patch we find a high link failure rate (&gt;5%) on certain
IMX6 boards at various temperatures.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: fix overflow in __pci_hose_bus_to_phys w/ large RAM</title>
<updated>2014-08-14T09:38:47+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-08-11T22:09:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d878c9a932eae626aced58128357fc6155f88739'/>
<id>d878c9a932eae626aced58128357fc6155f88739</id>
<content type='text'>
If a 32-bit system has 2GB of RAM, and the base address of that RAM is
2GB, then start+size will overflow a 32-bit value (to a value of 0).

To avoid such an overflow, convert __pci_hose_bus_to_phys() to calculate
the offset of a bus address into a PCI region, rather than comparing a
bus address against the end of a PCI region.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If a 32-bit system has 2GB of RAM, and the base address of that RAM is
2GB, then start+size will overflow a 32-bit value (to a value of 0).

To avoid such an overflow, convert __pci_hose_bus_to_phys() to calculate
the offset of a bus address into a PCI region, rather than comparing a
bus address against the end of a PCI region.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint</title>
<updated>2014-07-22T23:25:54+00:00</updated>
<author>
<name>Zang Roy-R61911</name>
<email>tie-fei.zang@freescale.com</email>
</author>
<published>2014-06-12T19:49:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=32514d259bf37cc92872aeb0624b75f600e7fb3a'/>
<id>32514d259bf37cc92872aeb0624b75f600e7fb3a</id>
<content type='text'>
Even u-boot boots up, the pcie link may not setup correctly when
Freescale SOC acts as endpoint.
So change the link status from 'no link' to 'undetermined' to
reduce the confusion.
The link status can check from host side eventually.

Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Even u-boot boots up, the pcie link may not setup correctly when
Freescale SOC acts as endpoint.
So change the link status from 'no link' to 'undetermined' to
reduce the confusion.
The link status can check from host side eventually.

Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fsl/pci: Add workaround for erratum A-005434</title>
<updated>2014-05-16T21:24:26+00:00</updated>
<author>
<name>Chunhe Lan</name>
<email>Chunhe.Lan@freescale.com</email>
</author>
<published>2014-05-07T02:50:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f1a96ec1a9920854c3308a062caca0b339bd1e3b'/>
<id>f1a96ec1a9920854c3308a062caca0b339bd1e3b</id>
<content type='text'>
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.

Signed-off-by: Minghuan Lian &lt;Minghuan.Lian@freescale.com&gt;
Signed-off-by: Chunhe Lan &lt;Chunhe.Lan@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.

Signed-off-by: Minghuan Lian &lt;Minghuan.Lian@freescale.com&gt;
Signed-off-by: Chunhe Lan &lt;Chunhe.Lan@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-arm into master</title>
<updated>2014-04-04T09:35:30+00:00</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2014-04-04T09:35:30+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1cad23c5f471d695bed1e3907e30caee3c2a3056'/>
<id>1cad23c5f471d695bed1e3907e30caee3c2a3056</id>
<content type='text'>
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Conflicts:
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
	arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: mx6: Implement power callback</title>
<updated>2014-03-31T16:28:50+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2014-03-23T21:45:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a778aeae051c96319855584c87d1dc3ca7257744'/>
<id>a778aeae051c96319855584c87d1dc3ca7257744</id>
<content type='text'>
Implement a callback to toggle the slot power supply. The callback
can be overriden in case some more complex power supply for the slot
was implemented in hardware, yet for the usual case, one can define
a GPIO which toggles the power to the slot.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Cc: Liu Ying &lt;Ying.Liu@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Implement a callback to toggle the slot power supply. The callback
can be overriden in case some more complex power supply for the slot
was implemented in hardware, yet for the usual case, one can define
a GPIO which toggles the power to the slot.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Cc: Liu Ying &lt;Ying.Liu@freescale.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
