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<title>u-boot.git/drivers/pci, branch v2015.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2015.01-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2015.01-rc2'/>
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<updated>2014-11-23T11:49:01Z</updated>
<entry>
<title>pci: Honour pci_skip_dev()</title>
<updated>2014-11-23T11:49:01Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-11-13T01:26:49Z</published>
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<id>urn:sha1:4efe52bf23c96cee7052273bd8549caee4d0fdc2</id>
<content type='text'>
When enumerating devices, honour the pci_skip_dev() function. This can
be used by PCI controller drivers to restrict which devices will be
probed.

This is required by the NVIDIA Tegra PCIe controller driver, which will
fail with a data abort exception if an access is attempted to a device
number larger than 0 outside of bus 0. pci_skip_dev() is therefore
implemented to prevent any such accesses.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>linux/kernel.h: sync min, max, min3, max3 macros with Linux</title>
<updated>2014-11-23T11:48:30Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-11-06T18:03:31Z</published>
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<id>urn:sha1:b41411954d4ccf6ddaa581178462017557b82b5d</id>
<content type='text'>
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Acked-by: Pavel Machek &lt;pavel@denx.de&gt;
Acked-by: Lukasz Majewski &lt;l.majewski@samsung.com&gt;
Tested-by: Lukasz Majewski &lt;l.majewski@samsung.com&gt;
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>pci: use __weak</title>
<updated>2014-10-25T11:01:59Z</updated>
<author>
<name>Jeroen Hofstee</name>
<email>jeroen@myspectrum.nl</email>
</author>
<published>2014-10-08T20:57:27Z</published>
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<id>urn:sha1:7b19fd6d9f64230eed2595442dbf85116685acc9</id>
<content type='text'>
Signed-off-by: Jeroen Hofstee &lt;jeroen@myspectrum.nl&gt;
</content>
</entry>
<entry>
<title>kconfig: add blank Kconfig files</title>
<updated>2014-09-24T22:30:28Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-09-16T07:32:58Z</published>
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<id>urn:sha1:ed36323f6d217050f82a2200475959b8557a47e4</id>
<content type='text'>
This would be useful to start moving various config options.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pcie_imx: Add mx6solox support</title>
<updated>2014-09-09T15:24:49Z</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2014-08-25T17:26:45Z</published>
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<id>urn:sha1:1b8ad74a6f8cea55a727dc4b399baac46d0daef1</id>
<content type='text'>
Let PCI on mx6solox also be supported.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
</entry>
<entry>
<title>pci: add support for board_pci_fixup_dev function</title>
<updated>2014-09-09T14:15:02Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2014-08-08T05:49:56Z</published>
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<id>urn:sha1:0991866cf7a10d4868aa2a10940b4def0f68cc50</id>
<content type='text'>
Some board-level drivers may wish to have per-device fixup functions
for PCI devices.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://www.denx.de/git/u-boot-imx</title>
<updated>2014-08-29T15:06:51Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-08-29T15:06:51Z</published>
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<id>urn:sha1:5a1095a830299aef8dd32495e505e92ab1749e89</id>
<content type='text'>
</content>
</entry>
<entry>
<title>pci: mx6: fix occasional link failures</title>
<updated>2014-08-20T10:37:15Z</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2014-08-08T05:57:29Z</published>
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<id>urn:sha1:5a82e1a21d1229e7e3d1c64187735794019e9a1b</id>
<content type='text'>
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.

Without this patch we find a high link failure rate (&gt;5%) on certain
IMX6 boards at various temperatures.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
Acked-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
</content>
</entry>
<entry>
<title>pci: fix overflow in __pci_hose_bus_to_phys w/ large RAM</title>
<updated>2014-08-14T09:38:47Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2014-08-11T22:09:28Z</published>
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<id>urn:sha1:d878c9a932eae626aced58128357fc6155f88739</id>
<content type='text'>
If a 32-bit system has 2GB of RAM, and the base address of that RAM is
2GB, then start+size will overflow a 32-bit value (to a value of 0).

To avoid such an overflow, convert __pci_hose_bus_to_phys() to calculate
the offset of a bus address into a PCI region, rather than comparing a
bus address against the end of a PCI region.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>fsl/pcie: Change 'no link' to 'undetermined' for pcie endpoint</title>
<updated>2014-07-22T23:25:54Z</updated>
<author>
<name>Zang Roy-R61911</name>
<email>tie-fei.zang@freescale.com</email>
</author>
<published>2014-06-12T19:49:23Z</published>
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<id>urn:sha1:32514d259bf37cc92872aeb0624b75f600e7fb3a</id>
<content type='text'>
Even u-boot boots up, the pcie link may not setup correctly when
Freescale SOC acts as endpoint.
So change the link status from 'no link' to 'undetermined' to
reduce the confusion.
The link status can check from host side eventually.

Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
</entry>
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