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<title>u-boot.git/drivers/pci, branch v2015.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>pci: pcie_imx: Fix hang on mx6qp</title>
<updated>2015-10-15T13:05:13+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2015-10-13T14:01:27+00:00</published>
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<id>aaf87f03ad709ff9f00819ef1eb001e878ad0a54</id>
<content type='text'>
PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
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<pre>
PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Acked-by: Stefano Babic &lt;sbabic@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: Fix expansion ROM programming for multi-function devices</title>
<updated>2015-10-08T18:09:09+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-10-07T09:13:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7445435fb32824e0cfd05beb7013be8f84e9ee09'/>
<id>7445435fb32824e0cfd05beb7013be8f84e9ee09</id>
<content type='text'>
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator
for multi-function devices. We should mask it off before using
it as the header type.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator
for multi-function devices. We should mask it off before using
it as the header type.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pci: Add an inline API to test if a device is on a PCI bus</title>
<updated>2015-09-17T01:53:52+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-09-11T10:24:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1e0f226362ffd2bd8c1a238af1d1b21ea86d3111'/>
<id>1e0f226362ffd2bd8c1a238af1d1b21ea86d3111</id>
<content type='text'>
Introduce device_is_on_pci_bus() which can be utilized by driver
to test if a device is on a PCI bus.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Introduce device_is_on_pci_bus() which can be utilized by driver
to test if a device is on a PCI bus.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pcie_imx: Use 'ms' for milliseconds</title>
<updated>2015-09-13T09:04:53+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@freescale.com</email>
</author>
<published>2015-09-10T23:45:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8f6edf6d30cc22a4231c5dd97a3bd82803d8f08c'/>
<id>8f6edf6d30cc22a4231c5dd97a3bd82803d8f08c</id>
<content type='text'>
milliseconds should be written as 'ms' instead of 'mS'.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Tested-by: Marek Vasut &lt;marex@denx.de&gt;
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<pre>
milliseconds should be written as 'ms' instead of 'mS'.

Signed-off-by: Fabio Estevam &lt;fabio.estevam@freescale.com&gt;
Tested-by: Marek Vasut &lt;marex@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pci: Allow a PCI bus to be found without an alias</title>
<updated>2015-09-09T13:48:03+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-09-01T00:55:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=983c6ba227e192c79b1df82853d8bacd40e1e989'/>
<id>983c6ba227e192c79b1df82853d8bacd40e1e989</id>
<content type='text'>
At present, until a PCI bus is probed, it cannot be found by its sequence
number unless it has an alias. This is the same with any device.

However with PCI this is more annoying than usual, since bus 0 is always the
same device.

Add a function that tries a little harder to locate PCI bus 0. This means
that PCI enumeration will happen automatically on the first access.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
At present, until a PCI bus is probed, it cannot be found by its sequence
number unless it has an alias. This is the same with any device.

However with PCI this is more annoying than usual, since bus 0 is always the
same device.

Add a function that tries a little harder to locate PCI bus 0. This means
that PCI enumeration will happen automatically on the first access.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci/layerscape: Setup mmu-masters property for the PCIe</title>
<updated>2015-09-02T02:49:27+00:00</updated>
<author>
<name>Varun Sethi</name>
<email>Varun.Sethi@freescale.com</email>
</author>
<published>2015-07-28T18:33:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6923b069bd50b3ac519b16b6ae6aabbd2984c391'/>
<id>6923b069bd50b3ac519b16b6ae6aabbd2984c391</id>
<content type='text'>
Setup mmu-masters property for the PCIe controllers. This would be
used by the Linux SMMU driver, while setting up stream ID table mappings
for the PCIe devices.

Signed-off-by: Varun Sethi &lt;Varun.Sethi@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
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<pre>
Setup mmu-masters property for the PCIe controllers. This would be
used by the Linux SMMU driver, while setting up stream ID table mappings
for the PCIe devices.

Signed-off-by: Varun Sethi &lt;Varun.Sethi@freescale.com&gt;
Reviewed-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pci: Optimize pci_uclass_post_bind()</title>
<updated>2015-08-26T14:54:17+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-08-24T08:14:01+00:00</published>
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<id>1887ed3ad6509a4ce411b7981dd27515e0c44bb7</id>
<content type='text'>
If there is no pci device listed in the device tree,
don't bother scanning the device tree.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
If there is no pci device listed in the device tree,
don't bother scanning the device tree.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pci: Save devfn without bus number in pci_uclass_child_post_bind()</title>
<updated>2015-08-26T14:54:13+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-08-20T13:40:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dce54dd6c70e6af9a1b506ed45c0cfc9a90fcc92'/>
<id>dce54dd6c70e6af9a1b506ed45c0cfc9a90fcc92</id>
<content type='text'>
In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr.
Mask bus number before save it to pplat-&gt;devfn.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr.
Mask bus number before save it to pplat-&gt;devfn.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: fsp: Call fsp_init_phase_pci() in pci_uclass_post_probe()</title>
<updated>2015-08-26T14:54:12+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-08-20T13:40:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=348b744b7c6528c0509e2a0b0740be3ce949497f'/>
<id>348b744b7c6528c0509e2a0b0740be3ce949497f</id>
<content type='text'>
Per Intel FSP specification, we should call FSP notify API to
inform FSP that PCI enumeration has been done so that FSP will
do any necessary initialization as required by the chipset's
BIOS Writer's Guide (BWG).

Unfortunately we have to put this call here as with driver model,
the enumeration is all done on a lazy basis as needed, so until
something is touched on PCI it won't happen.

Note we only call this after U-Boot is relocated and root bus has
finished probing.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Per Intel FSP specification, we should call FSP notify API to
inform FSP that PCI enumeration has been done so that FSP will
do any necessary initialization as required by the chipset's
BIOS Writer's Guide (BWG).

Unfortunately we have to put this call here as with driver model,
the enumeration is all done on a lazy basis as needed, so until
something is touched on PCI it won't happen.

Note we only call this after U-Boot is relocated and root bus has
finished probing.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pci: Support selected device/driver binding before relocation</title>
<updated>2015-08-26T14:54:11+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-08-20T13:40:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=08fc7b8fac1d27d7e9f964309cbc32de0abd2c0d'/>
<id>08fc7b8fac1d27d7e9f964309cbc32de0abd2c0d</id>
<content type='text'>
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. But we won't
bind all devices found during the enumeration. Only devices whose
driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic
devices except bridges won't be bound.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. But we won't
bind all devices found during the enumeration. Only devices whose
driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic
devices except bridges won't be bound.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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