u-boot.git/drivers/pci, branch v2016.01-rc1

Merge branch 'master' of git://git.denx.de/u-boot-tegra

2015-11-13T00:32:51Z

pci: fix checking PCI_REGION_MEM in pci_hose_phys_to_bus()

2015-11-12T18:19:03Z

When converting between PCI bus and phys addresses, a two pass search was introduced with preference to non-PCI_REGION_SYS_MEMORY regions. See commit 2d43e873a29ca4959ba6a30fc7fb396d3fd0dccf. However, since PCI_REGION_MEM is defined as 0, the if statement was always asserted true: ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) This patch uses PCI_REGION_TYPE bit to check if the region is PCI_REGION_MEM: ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) Signed-off-by: Cheng Gu Reviewed-by: Bin Meng

pci: tegra: add/enable support for Tegra210

2015-11-12T16:21:05Z

This needs a separate compatible value from Tegra124 since the new HW version has bugs that would prevent a driver for previous HW versions from operating at all. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren

pci: tegra: call tegra_pcie_board_init() earlier

2015-11-12T16:21:05Z

The board PCI setup code may control regulators that are required simply to bring up the PCI controller itself (or PLLs, IOs, ... it uses). Move the call to this function earlier so that all board-provided resources are ready early enough for everything to work. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren

pci: tegra: implement PCA enable workaround

2015-11-12T16:21:05Z

Tegra210's PCIe controller has a bug that requires the PCA (performance counter) feature to be enabled. If this isn't done, accesses to device configuration space will hang the chip for tens of seconds. Implement the workaround. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren

pci: tegra: use #address-/size-cells from DT

2015-11-12T16:21:05Z

The number of cells used by each entry in the DT ranges property is determined by the #address-cells/#size-cells properties. Fix the code to respect this. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren

pci: tegra: clip RAM size to 32-bits

2015-11-12T16:21:05Z

Tegra peripherals can generally access a 32-bit physical address space, and I believe this applies to PCIe. Clip the PCI region that refers to DRAM so it fits into 32-bits to avoid issues. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren

armv8/fsl_lsch3: Change arch to fsl-layerscape

2015-10-29T17:34:00Z

There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu Signed-off-by: Hou Zhiqiang Signed-off-by: Gong Qianyu Reviewed-by: York Sun

dm: pci: Enable VGA address forwarding on bridges

2015-10-21T13:46:25Z

To support graphics card behind a PCI bridge, the bridge control register (offset 0x3e) in the configuration space must turn on VGA address forwarding. Signed-off-by: Bin Meng Acked-by: Simon Glass

dm: pci: Fix pci_last_busno() to return the real last bus no

2015-10-21T13:46:25Z

Currently pci_last_busno() only checks the last bridge device under the first UCLASS_PCI device. This is not the case when there are multiple bridge devices. Signed-off-by: Bin Meng Acked-by: Simon Glass