<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/pci, branch v2016.01-rc4</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2016.01-rc4</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2016.01-rc4'/>
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<updated>2015-12-09T09:44:56Z</updated>
<entry>
<title>x86: Remove HAVE_ACPI_RESUME</title>
<updated>2015-12-09T09:44:56Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-11-26T01:46:09Z</published>
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<id>urn:sha1:789fa275b3750e60c60cb3d18eabc9467892c257</id>
<content type='text'>
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: pci: Disable PCI compatibility functions by default</title>
<updated>2015-12-01T13:26:38Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-27T02:51:30Z</published>
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<id>urn:sha1:3ba5f74a541f77bfb6904e684e2cf0bfad005106</id>
<content type='text'>
We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: Move common auto-config functions to a common file</title>
<updated>2015-12-01T13:26:37Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-27T02:51:23Z</published>
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<id>urn:sha1:011e9482959afb40319b3e965da9c3e356c6d679</id>
<content type='text'>
Some functions will be used by driver model and legacy PCI code. To avoid
duplication, put these in a separate, shared file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: Rename pci_auto.c to pci_auto_old.c</title>
<updated>2015-12-01T13:26:37Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-27T02:51:22Z</published>
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<id>urn:sha1:76a8b6a58af8f9477d46c0bf32ce02e6d75fff86</id>
<content type='text'>
This file should not be used with driver model as it has lots of legacy/
compatibility functions. Rename it to make this clear.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: tegra: pci: Convert tegra boards to driver model for PCI</title>
<updated>2015-12-01T13:26:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-20T03:27:02Z</published>
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<id>urn:sha1:e81ca88451cf4b692fede0b9c2e3444e4b61e139</id>
<content type='text'>
Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: Add a function to find the regions for a PCI bus</title>
<updated>2015-12-01T13:26:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-20T03:27:01Z</published>
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<id>urn:sha1:f9260336d0eb3e41ced18f6408e90a32c8825f6c</id>
<content type='text'>
This function looks up the controller and returns a pointer to each region
type.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: Add a function to get the controller for a bus</title>
<updated>2015-12-01T13:26:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-20T03:27:00Z</published>
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<id>urn:sha1:9f60fb0db4b70c65760cb1799b76de1c9b71644d</id>
<content type='text'>
A PCI bus may be a bridge device where the controller is the bridge's
parent. Add a function to return the controller device, given a PCI device.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: Add functions to emulate 8- and 16-bit access</title>
<updated>2015-12-01T13:26:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-20T03:26:59Z</published>
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<id>urn:sha1:9289db6c60bc9caa285fc6459db9236d92ba94f6</id>
<content type='text'>
Provide a few functions to support using 32-bit access to emulate 8- and
16-bit access.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: Support decoding ranges with duplicate entries</title>
<updated>2015-12-01T13:26:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-20T03:26:58Z</published>
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<id>urn:sha1:9526d83ac5a39bfa3dc4c07a242aa052093744b5</id>
<content type='text'>
At present we add a new resource entry for every range entry. But some range
entries refer to configuration regions. To make this work, avoid adding two
regions of the same type. The later ranges will overwrite the earlier
(configuration) ones.

There does not seem to be a way to distinguish the configuration ranges
other than by ordering (as per the device tree binding).

We could perhaps instead just store one region of each type in a simple
array. Once we are sure that we don't need to support multiple regions, we
could change this. It would be easier to do it when all drivers are
converted to use driver model for PCI.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: Set up the SDRAM mapping correctly</title>
<updated>2015-12-01T13:26:36Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-11-20T03:26:57Z</published>
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<id>urn:sha1:2084c5af6dc03b500622ae8844bc69cc5a8e51fb</id>
<content type='text'>
SDRAM doesn't always start at 0. Adjust the region mapping so that it works
on platforms where SDRAM is somewhere else.

This needs testing on other platforms.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
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