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<title>u-boot.git/drivers/pci, branch v2016.07-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2016.07-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2016.07-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-06-03T21:12:10Z</updated>
<entry>
<title>pcie/layerscape: fix bug in bus number computation when setting msi-map</title>
<updated>2016-06-03T21:12:10Z</updated>
<author>
<name>Bogdan Purcareata</name>
<email>bogdan.purcareata@nxp.com</email>
</author>
<published>2016-05-17T07:18:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3378727d13dac410d8ef2d8426d4c9bfc4974405'/>
<id>urn:sha1:3378727d13dac410d8ef2d8426d4c9bfc4974405</id>
<content type='text'>
When multiple PCI cards are present in an ls2080a board, the second
card does not get its msi-map set up properly due to a bug in
computing the bus number.

The bus number returned by PCI_BDF() is not the actual PCI bus
number, but instead represents a global u-boot PCI bus number. A
given bus number is relative to hose-&gt;first_busno, so that has to be
subtracted from the PCI device id.

Signed-off-by: Bogdan Purcareata &lt;bogdan.purcareata@nxp.com&gt;
Acked-by: Stuart Yoder &lt;stuart.yoder@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: Drop CONFIG_SYS_SCSI_SCAN_BUS_REVERSE</title>
<updated>2016-05-17T15:54:43Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-01T17:35:51Z</published>
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<id>urn:sha1:cf63084492377108698619f6d33967af2119e584</id>
<content type='text'>
This option is not used by any board. Drop it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci: tegra: fix DM conversion issues on Tegra20</title>
<updated>2016-05-04T20:31:04Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-04-20T21:46:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f5c6db84e71c60bfc7ae746bfb2cd1090d0b8765'/>
<id>urn:sha1:f5c6db84e71c60bfc7ae746bfb2cd1090d0b8765</id>
<content type='text'>
Tegra20's PCIe controller has a couple of quirks. There are workarounds in
the driver for these, but they don't work after the DM conversion:

1) The PCI_CLASS value is wrong in HW.

This is worked around in pci_tegra_read_config() by patching up the value
read from that register. Pre-DM, the PCIe core always read this via a
16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used,
so we need to check for offset 0x8 instead. Mask the offset value back to
32-bit alignment to make this work in all cases.

2) Accessing devices other than dev 1 causes a data abort.

Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code
called during enumeration while iterating over a bus. The DM PCIe core
doesn't use this function. Instead, enhance tegra_pcie_conf_address() to
validate the bdf being accessed, and refuse to access invalid devices.
Since pci_skip_dev() isn't used, delete it.

I've also validated that both these WARs are only needed for Tegra20, by
testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in
conditionally.

Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model for PCI")
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;treding@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>pci: Device scanning range fix</title>
<updated>2016-04-25T19:10:43Z</updated>
<author>
<name>Yoshinori Sato</name>
<email>ysato@users.sourceforge.jp</email>
</author>
<published>2016-04-25T06:41:01Z</published>
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<id>urn:sha1:6d9f5b035d73129fe0ba4c0d28af55ee565e2490</id>
<content type='text'>
The terminal condition in the area where a PCI device is scanned is wrong,
and 1f.7 isn't scanned.

Signed-off-by: Yoshinori Sato &lt;ysato@users.sourceforge.jp&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci/layerscape: set LUT and msi-map for discovered PCI devices</title>
<updated>2016-03-21T19:42:13Z</updated>
<author>
<name>Stuart Yoder</name>
<email>stuart.yoder@nxp.com</email>
</author>
<published>2016-03-10T16:52:30Z</published>
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<id>urn:sha1:5e8e27b743a650aebc3d79823cbd8443ca12d4b8</id>
<content type='text'>
msi-map properties are used to tell an OS how PCI requester IDs are
mapped to ARM SMMU stream IDs.

for all PCI devices discovered in a system:
  -allocate a LUT (look-up-table) entry in that PCI controller
  -allocate a stream ID for the device
  -program and enable a LUT entry (maps PCI requester id to stream ID)
  -set the msi-map property on the controller reflecting the
   LUT mapping

basic bus scanning loop/logic was taken from drivers/pci/pci.c
pci_hose_scan_bus().

Signed-off-by: Stuart Yoder &lt;stuart.yoder@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>armv8: ls2080a: remove obsolete stream ID partitioning support</title>
<updated>2016-03-21T19:42:12Z</updated>
<author>
<name>Stuart Yoder</name>
<email>stuart.yoder@nxp.com</email>
</author>
<published>2016-03-10T16:52:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2d97fbb4c4c7c576b224aaa38465816e0edbd4d6'/>
<id>urn:sha1:2d97fbb4c4c7c576b224aaa38465816e0edbd4d6</id>
<content type='text'>
Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.

Signed-off-by: Stuart Yoder &lt;stuart.yoder@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
</entry>
<entry>
<title>pci: Correct a few comments and nits</title>
<updated>2016-03-17T02:27:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-07T02:27:53Z</published>
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<id>urn:sha1:4974a6ff048fecba6077bf3101c6aba830e038c7</id>
<content type='text'>
Two comments are missing a parameter and there is an extra blank line. Also
two of the region access macros are misnamed. Correct these problems.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci: Add functions to update PCI configuration registers</title>
<updated>2016-03-17T02:27:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-07T02:27:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=319dba1f4d7bf2c82be1c5b0858c4b1c3d8b4cfe'/>
<id>urn:sha1:319dba1f4d7bf2c82be1c5b0858c4b1c3d8b4cfe</id>
<content type='text'>
It is common to read a config register value, clear and set some bits, then
write back the updated value. Add functions to do this in one step, for
convenience.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: pci: Break out the common region display code</title>
<updated>2016-03-14T21:34:50Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-02-29T22:25:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=02c80a0e138ff656219050afa6ecf2368e6c9293'/>
<id>urn:sha1:02c80a0e138ff656219050afa6ecf2368e6c9293</id>
<content type='text'>
Each region is displayed in almost the same way. Break out this common code
into its own function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dm: Use uclass_first_device_err() where it is useful</title>
<updated>2016-03-14T21:34:50Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-02-11T20:23:26Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3f603cbbb8e175e545d6037a783e1ef82bab30f9'/>
<id>urn:sha1:3f603cbbb8e175e545d6037a783e1ef82bab30f9</id>
<content type='text'>
Use this new function in places where it simplifies the code.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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