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<title>u-boot.git/drivers/pci, branch v2017.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Merge git://git.denx.de/u-boot-dm</title>
<updated>2017-04-04T13:18:57+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-04-04T13:18:57+00:00</published>
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<entry>
<title>pcie-layerscape: Fixup iommu-map property of pci node</title>
<updated>2017-03-28T17:54:09+00:00</updated>
<author>
<name>Bharat Bhushan</name>
<email>bharat.bhushan@nxp.com</email>
</author>
<published>2017-03-22T06:42:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=78be6222b01efa12d9267876ad1d1d0daf38dfa0'/>
<id>78be6222b01efa12d9267876ad1d1d0daf38dfa0</id>
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This patch fixup iommu-map property on pci node to have a valid
mapping of requester-id to stream-id. The requester-id to stream-id
mapping is based on PCI-LUT table initialization.

Signed-off-by: Bharat Bhushan &lt;Bharat.Bhushan@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
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This patch fixup iommu-map property on pci node to have a valid
mapping of requester-id to stream-id. The requester-id to stream-id
mapping is based on PCI-LUT table initialization.

Signed-off-by: Bharat Bhushan &lt;Bharat.Bhushan@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
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</entry>
<entry>
<title>pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs</title>
<updated>2017-03-28T17:52:41+00:00</updated>
<author>
<name>Bharat Bhushan</name>
<email>bharat.bhushan@nxp.com</email>
</author>
<published>2017-03-22T06:36:30+00:00</published>
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<content type='text'>
Layerscape Chasis-2 also uses same PCIe controller as Chasis-3
and have similar PCI-Lut.

Signed-off-by: Bharat Bhushan &lt;bharat.bhushan@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
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<pre>
Layerscape Chasis-2 also uses same PCIe controller as Chasis-3
and have similar PCI-Lut.

Signed-off-by: Bharat Bhushan &lt;bharat.bhushan@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
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</entry>
<entry>
<title>pci: layerscape: Fixup device tree node for ls2088a</title>
<updated>2017-03-28T16:22:18+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2017-03-03T04:35:10+00:00</published>
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<content type='text'>
LS2088A and its variants have different PCIe node than LS2080A.
The compatible string is updated accordingly.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
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<pre>
LS2088A and its variants have different PCIe node than LS2080A.
The compatible string is updated accordingly.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
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</entry>
<entry>
<title>pci: layerscape: add LS2088A series SoC pcie support</title>
<updated>2017-03-28T16:21:13+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2017-03-03T04:35:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3d8553f0a3eea4a0b9b2f6b3ce247fee9c4232f2'/>
<id>3d8553f0a3eea4a0b9b2f6b3ce247fee9c4232f2</id>
<content type='text'>
The LS2088A series SoCs has different physical memory map address and
CCSR registers address against LS2080A series SoCs.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
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<pre>
The LS2088A series SoCs has different physical memory map address and
CCSR registers address against LS2080A series SoCs.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
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</entry>
<entry>
<title>pci: layerscape: enable PCIe config ready</title>
<updated>2017-03-28T16:06:11+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2017-02-10T07:42:11+00:00</published>
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In EP mode, to enable accesses from the Root Complex, the
CONFIG_READY bit must be set, otherwise any config attempts
from the Root Complex will be returned with config retry
status (CRS).

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Signed-off-by: Minghuan Lian &lt;Minghuan.Lian@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
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<pre>
In EP mode, to enable accesses from the Root Complex, the
CONFIG_READY bit must be set, otherwise any config attempts
from the Root Complex will be returned with config retry
status (CRS).

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Signed-off-by: Minghuan Lian &lt;Minghuan.Lian@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
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</entry>
<entry>
<title>pci: correct a function description</title>
<updated>2017-03-26T19:22:58+00:00</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2017-03-22T08:07:24+00:00</published>
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<id>0367bd4d605fa17b0e8ee8b45bc7afa6bd2307f9</id>
<content type='text'>
In the description of function pci_match_one_id(), there are some
problems on arguments list and return value description, so correct
them.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
In the description of function pci_match_one_id(), there are some
problems on arguments list and return value description, so correct
them.

Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>mvebu: pcie: Add support for GPIO reset for PCIe device</title>
<updated>2017-03-23T07:45:25+00:00</updated>
<author>
<name>Konstantin Porotchkin</name>
<email>kostap@marvell.com</email>
</author>
<published>2017-02-08T15:34:13+00:00</published>
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<id>130b53ec79f3f1b1349d409f08f1f17e68a15f96</id>
<content type='text'>
Add support for "marvell,reset-gpio" property to mvebu DW PCIe
driver.
This option is valid when CONFIG_DM_GPIO=y

Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Signed-off-by: Rabeeh Khoury &lt;rabeeh@solid-run.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Neta Zur Hershkovits &lt;neta@marvell.com&gt;
Cc: Igal Liberman &lt;igall@marvell.com&gt;
Cc: Haim Boot &lt;hayim@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
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<pre>
Add support for "marvell,reset-gpio" property to mvebu DW PCIe
driver.
This option is valid when CONFIG_DM_GPIO=y

Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986
Signed-off-by: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Signed-off-by: Rabeeh Khoury &lt;rabeeh@solid-run.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Neta Zur Hershkovits &lt;neta@marvell.com&gt;
Cc: Igal Liberman &lt;igall@marvell.com&gt;
Cc: Haim Boot &lt;hayim@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>dm: core: Replace of_offset with accessor</title>
<updated>2017-02-08T13:12:14+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-01-17T23:52:55+00:00</published>
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<content type='text'>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>x86: Don't try to run the VGA BIOS in 64-bit mode</title>
<updated>2017-02-06T03:38:46+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-01-16T14:04:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=05cbd985c0b9b5319355fcd562f5665d5fcb8652'/>
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<content type='text'>
This is not supported, so disable it for now.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
This is not supported, so disable it for now.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
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</content>
</entry>
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