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<title>u-boot.git/drivers/pci, branch v2018.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>libfdt: move headers to &lt;linux/libfdt.h&gt; and &lt;linux/libfdt_env.h&gt;</title>
<updated>2018-03-05T15:16:28+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2018-03-04T16:20:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b08c8c4870831c9315dcae237772238e80035bd5'/>
<id>b08c8c4870831c9315dcae237772238e80035bd5</id>
<content type='text'>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -&gt; include/linux/libfdt.h
  include/libfdt_env.h     -&gt; include/linux/libfdt_env.h

and replaces include directives:
  #include &lt;libfdt.h&gt;      -&gt; #include &lt;linux/libfdt.h&gt;
  #include &lt;libfdt_env.h&gt;  -&gt; #include &lt;linux/libfdt_env.h&gt;

Reported-by: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
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<pre>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -&gt; include/linux/libfdt.h
  include/libfdt_env.h     -&gt; include/linux/libfdt_env.h

and replaces include directives:
  #include &lt;libfdt.h&gt;      -&gt; #include &lt;linux/libfdt.h&gt;
  #include &lt;libfdt_env.h&gt;  -&gt; #include &lt;linux/libfdt_env.h&gt;

Reported-by: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>pci: Fix decode regions for memory banks</title>
<updated>2018-02-23T15:40:50+00:00</updated>
<author>
<name>Bernhard Messerklinger</name>
<email>bernhard.messerklinger@br-automation.com</email>
</author>
<published>2018-02-15T07:59:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=664758c3dd1cf9c892ce98112e629cb032ac64aa'/>
<id>664758c3dd1cf9c892ce98112e629cb032ac64aa</id>
<content type='text'>
Since memory banks may not be located behind each other we need to add
them separately.

Signed-off-by: Bernhard Messerklinger &lt;bernhard.messerklinger@br-automation.com&gt;
Reviewed-by: Hannes Schmelzer &lt;hannes.schmelzer@br-automation.com&gt;
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<pre>
Since memory banks may not be located behind each other we need to add
them separately.

Signed-off-by: Bernhard Messerklinger &lt;bernhard.messerklinger@br-automation.com&gt;
Reviewed-by: Hannes Schmelzer &lt;hannes.schmelzer@br-automation.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: rmobile: Add RCar Gen2 PCIe controller driver</title>
<updated>2018-01-27T19:38:53+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-01-18T13:35:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5f14f7d783f1a3a2e8085738a31b82580addf7b9'/>
<id>5f14f7d783f1a3a2e8085738a31b82580addf7b9</id>
<content type='text'>
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs.
The PCIe on Gen2 is used both to connect external PCIe peripherals as
well as access the on-SoC USB EHCI controller.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
</content>
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<pre>
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs.
The PCIe on Gen2 is used both to connect external PCIe peripherals as
well as access the on-SoC USB EHCI controller.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: pci: imx: fix enumeration logic error</title>
<updated>2018-01-12T13:28:04+00:00</updated>
<author>
<name>Koen Vandeputte</name>
<email>koen.vandeputte@ncentric.com</email>
</author>
<published>2018-01-04T13:54:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f57263ee9bb8b5d9f39b48d09d21114c9dbb6a02'/>
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<content type='text'>
By default, the subordinate is set equally to the secondary bus (1) when
the RC boots, and does not alter afterwards.

This means that theoretically, the highest bus reachable downstream is
bus 1.

Force the PCIe RC subordinate to 0xff, otherwise no downstream
devices will be detected behind bus 1 if the booting OS does not allow
enumerating a higher busnr than the subordinate value of the primary
bus.

Signed-off-by: Koen Vandeputte &lt;koen.vandeputte@ncentric.com&gt;
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<pre>
By default, the subordinate is set equally to the secondary bus (1) when
the RC boots, and does not alter afterwards.

This means that theoretically, the highest bus reachable downstream is
bus 1.

Force the PCIe RC subordinate to 0xff, otherwise no downstream
devices will be detected behind bus 1 if the booting OS does not allow
enumerating a higher busnr than the subordinate value of the primary
bus.

Signed-off-by: Koen Vandeputte &lt;koen.vandeputte@ncentric.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>pci: imx: request gpio before use</title>
<updated>2018-01-12T13:28:04+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2018-01-02T10:27:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=67b71df277196f1649c366e52545f5bfccf56e03'/>
<id>67b71df277196f1649c366e52545f5bfccf56e03</id>
<content type='text'>
Before use GPIO, we need to request gpio first. Free gpio after use.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Stefano Babic &lt;ssbabic@denx.de&gt;
</content>
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<pre>
Before use GPIO, we need to request gpio first. Free gpio after use.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Reviewed-by: Stefano Babic &lt;ssbabic@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>PCI: Drop CONFIG_TSI108_PCI</title>
<updated>2018-01-10T13:05:49+00:00</updated>
<author>
<name>Tuomas Tynkkynen</name>
<email>tuomas@tuxera.com</email>
</author>
<published>2017-12-18T22:28:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=55acf49eaba0a05d1ca1406d60ec645e992b4641'/>
<id>55acf49eaba0a05d1ca1406d60ec645e992b4641</id>
<content type='text'>
Last user of this option went away in 2015 in commit:
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")

Signed-off-by: Tuomas Tynkkynen &lt;tuomas@tuxera.com&gt;
</content>
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<pre>
Last user of this option went away in 2015 in commit:
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")

Signed-off-by: Tuomas Tynkkynen &lt;tuomas@tuxera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Update Paul Burton's email address</title>
<updated>2017-11-28T20:59:30+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@mips.com</email>
</author>
<published>2017-10-30T23:58:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c5bf161facd5c10348c7e3963af6bd1cc9a79167'/>
<id>c5bf161facd5c10348c7e3963af6bd1cc9a79167</id>
<content type='text'>
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (&amp; tools such as get_maintainer.pl
when examining history) will use the new address.

Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: u-boot@lists.denx.de
</content>
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<pre>
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (&amp; tools such as get_maintainer.pl
when examining history) will use the new address.

Signed-off-by: Paul Burton &lt;paul.burton@mips.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: u-boot@lists.denx.de
</pre>
</div>
</content>
</entry>
<entry>
<title>dm: pci: change bus number register setting compliant with Linux</title>
<updated>2017-11-17T15:53:45+00:00</updated>
<author>
<name>Minghuan Lian</name>
<email>Minghuan.Lian@nxp.com</email>
</author>
<published>2017-10-20T02:45:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3977dcd559e392b9a2f3c69e317527cbe8b6ae15'/>
<id>3977dcd559e392b9a2f3c69e317527cbe8b6ae15</id>
<content type='text'>
This patch is to change U-Boot PCI bus assignement compliant with Linux.
It means each PCIe controller's bus number is 0, not the current maximum
PCI bus number, when start to scan this controller.

Signed-off-by: Minghuan Lian &lt;Minghuan.Lian@nxp.com&gt;
Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
This patch is to change U-Boot PCI bus assignement compliant with Linux.
It means each PCIe controller's bus number is 0, not the current maximum
PCI bus number, when start to scan this controller.

Signed-off-by: Minghuan Lian &lt;Minghuan.Lian@nxp.com&gt;
Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: mvebu: Increase size of PCIe default mapping</title>
<updated>2017-11-16T10:43:15+00:00</updated>
<author>
<name>VlaoMao</name>
<email>vlaomao@gmail.com</email>
</author>
<published>2017-09-22T15:49:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=49b23e035d96227e1d760e26a50688804de175ed'/>
<id>49b23e035d96227e1d760e26a50688804de175ed</id>
<content type='text'>
Increase size PCI memory mapping from 32MiB to 128MiB.

Signed-off-by: VlaoMao &lt;vlaomao@gmail.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
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<pre>
Increase size PCI memory mapping from 32MiB to 128MiB.

Signed-off-by: VlaoMao &lt;vlaomao@gmail.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: pci: imx: fix imx_pcie_remove function</title>
<updated>2017-10-12T15:56:28+00:00</updated>
<author>
<name>Sven-Ola Tuecke</name>
<email>sven-ola.tuecke@numberfour.eu</email>
</author>
<published>2017-10-05T11:46:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b2915ba25e350caa79a13a1cd3513eb82709e1f9'/>
<id>b2915ba25e350caa79a13a1cd3513eb82709e1f9</id>
<content type='text'>
We have at least a minor count of boards, that failed to re-initialize
PCI express in the Linux kernel. Typical failure rate is 20% on affected
boards. This is mitigated by commit 6ecbe1375671 ("drivers: pci: imx:
add imx_pcie_remove function").

However, at least on some i.MX6 custom boards, when calling
assert_core_reset() as part of the first-time PCIe init, read access
to PCIE_PL_PFLR simply hangs. Surround this readl() with
imx_pcie_fix_dabt_handler() does not help. For this reason, the forced
LTSSM detection is only used on the second assert_core_reset() that is
called shorly before starting the Linux kernel.

Signed-off-by: Sven-Ola Tuecke &lt;sven-ola.tuecke@numberfour.eu&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Tested-by: David Müller &lt;d.mueller@elsoft.ch&gt;
</content>
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<pre>
We have at least a minor count of boards, that failed to re-initialize
PCI express in the Linux kernel. Typical failure rate is 20% on affected
boards. This is mitigated by commit 6ecbe1375671 ("drivers: pci: imx:
add imx_pcie_remove function").

However, at least on some i.MX6 custom boards, when calling
assert_core_reset() as part of the first-time PCIe init, read access
to PCIE_PL_PFLR simply hangs. Surround this readl() with
imx_pcie_fix_dabt_handler() does not help. For this reason, the forced
LTSSM detection is only used on the second assert_core_reset() that is
called shorly before starting the Linux kernel.

Signed-off-by: Sven-Ola Tuecke &lt;sven-ola.tuecke@numberfour.eu&gt;
Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Tested-by: David Müller &lt;d.mueller@elsoft.ch&gt;
</pre>
</div>
</content>
</entry>
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