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<title>u-boot.git/drivers/pci, branch v2018.05-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2018.05-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2018.05-rc2'/>
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<updated>2018-04-16T14:38:52Z</updated>
<entry>
<title>pci: video: Only print out when everything is OK</title>
<updated>2018-04-16T14:38:52Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-04-12T05:02:18Z</published>
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<id>urn:sha1:611309383d19ec806bdf38bea70fc2d7636ae64f</id>
<content type='text'>
If video initialization fails, the "Video:" output message will be
mixed with the next console log. Change to print out such message
only when everything is OK, which improves the boot log readability.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-marvell</title>
<updated>2018-03-30T22:18:22Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-03-30T22:18:22Z</published>
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<id>urn:sha1:f3b623fa52ce5c67732ea2d789d5e21667e88db3</id>
<content type='text'>
</content>
</entry>
<entry>
<title>arm64: a37xx: pci: add support for aardvark pcie driver</title>
<updated>2018-03-30T10:52:49Z</updated>
<author>
<name>Wilson Ding</name>
<email>dingwei@marvell.com</email>
</author>
<published>2018-03-26T07:57:29Z</published>
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<id>urn:sha1:e51f2b14c4936daf3e3040bddb15f63d35e6d988</id>
<content type='text'>
This patch introduced the Aardvark PCIe driver based
driver model.
The PCIe driver is supposed to work in Root Complex
mode. It only supports X1 lane width.

Signed-off-by: Wilson Ding &lt;dingwei@marvell.com&gt;
Reviewed-on: http://vgitil04.il.marvell.com:8080/38725
Reviewed-by: Victor Gu &lt;xigu@marvell.com&gt;
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Tested-by: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>dm: pcie: designware: add correct ATU handling</title>
<updated>2018-03-30T10:52:48Z</updated>
<author>
<name>Igal Liberman</name>
<email>igall@marvell.com</email>
</author>
<published>2018-02-14T17:25:23Z</published>
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<id>urn:sha1:b8478fcd042686f7fe35edd30cc14f876762543c</id>
<content type='text'>
Currently, ATU (address translation unit) implementation doesn't
support translate addresses &gt; 32 bits.

This patch allows to configure ATU correctly for different
memory accesses (memory, configuration and IO).
The same approach is used in Linux Kernel.

Signed-off-by: Igal Liberman &lt;igall@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>dm: pci: Avoid setting a PCI region that has 0 size</title>
<updated>2018-03-30T08:05:08Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-03-27T07:46:06Z</published>
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<id>urn:sha1:ee1109bb45be4aaf057a44a70c9bdf2d7ff5bbc7</id>
<content type='text'>
It makes no sense to set a PCI region that has 0 size.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: pci: Check board information pointer in decode_regions()</title>
<updated>2018-03-30T08:05:08Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-03-27T07:46:05Z</published>
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<id>urn:sha1:1eaf7800b6b99b48e73eab56202cf1c7a0e19ac9</id>
<content type='text'>
PCI enumeration may happen very early on an x86 board. The board
information pointer should have been checked in decode_regions()
as its space may not be allocated yet.

With this commit, Intel Galileo board boots again.

Fixes: 664758c ("pci: Fix decode regions for memory banks")
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>libfdt: move headers to &lt;linux/libfdt.h&gt; and &lt;linux/libfdt_env.h&gt;</title>
<updated>2018-03-05T15:16:28Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2018-03-04T16:20:11Z</published>
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<id>urn:sha1:b08c8c4870831c9315dcae237772238e80035bd5</id>
<content type='text'>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -&gt; include/linux/libfdt.h
  include/libfdt_env.h     -&gt; include/linux/libfdt_env.h

and replaces include directives:
  #include &lt;libfdt.h&gt;      -&gt; #include &lt;linux/libfdt.h&gt;
  #include &lt;libfdt_env.h&gt;  -&gt; #include &lt;linux/libfdt_env.h&gt;

Reported-by: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>pci: Fix decode regions for memory banks</title>
<updated>2018-02-23T15:40:50Z</updated>
<author>
<name>Bernhard Messerklinger</name>
<email>bernhard.messerklinger@br-automation.com</email>
</author>
<published>2018-02-15T07:59:53Z</published>
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<id>urn:sha1:664758c3dd1cf9c892ce98112e629cb032ac64aa</id>
<content type='text'>
Since memory banks may not be located behind each other we need to add
them separately.

Signed-off-by: Bernhard Messerklinger &lt;bernhard.messerklinger@br-automation.com&gt;
Reviewed-by: Hannes Schmelzer &lt;hannes.schmelzer@br-automation.com&gt;
</content>
</entry>
<entry>
<title>pci: rmobile: Add RCar Gen2 PCIe controller driver</title>
<updated>2018-01-27T19:38:53Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@gmail.com</email>
</author>
<published>2018-01-18T13:35:35Z</published>
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<id>urn:sha1:5f14f7d783f1a3a2e8085738a31b82580addf7b9</id>
<content type='text'>
Add driver for the Renesas RCar PCIe controller present on Gen2 SoCs.
The PCIe on Gen2 is used both to connect external PCIe peripherals as
well as access the on-SoC USB EHCI controller.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
</content>
</entry>
<entry>
<title>drivers: pci: imx: fix enumeration logic error</title>
<updated>2018-01-12T13:28:04Z</updated>
<author>
<name>Koen Vandeputte</name>
<email>koen.vandeputte@ncentric.com</email>
</author>
<published>2018-01-04T13:54:34Z</published>
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<id>urn:sha1:f57263ee9bb8b5d9f39b48d09d21114c9dbb6a02</id>
<content type='text'>
By default, the subordinate is set equally to the secondary bus (1) when
the RC boots, and does not alter afterwards.

This means that theoretically, the highest bus reachable downstream is
bus 1.

Force the PCIe RC subordinate to 0xff, otherwise no downstream
devices will be detected behind bus 1 if the booting OS does not allow
enumerating a higher busnr than the subordinate value of the primary
bus.

Signed-off-by: Koen Vandeputte &lt;koen.vandeputte@ncentric.com&gt;
</content>
</entry>
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