u-boot.git/drivers/pci, branch v2020.01 Unnamed repository; edit this file 'description' to name the repository. drivers: pci: ignore disabled devices 2019-12-05T15:28:38+00:00 Michael Walle michael@walle.cc 2019-12-01T16:45:18+00:00 a6cd597a78dd9b7fcaba6fe4891f29e86646541b PCI devices may be disabled in the device tree. Devices which are probed by the device tree handle the "status" property and are skipped if disabled. Devices which are probed by the PCI enumeration don't check that property. Fix it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com> Tested-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
PCI devices may be disabled in the device tree. Devices which are probed
by the device tree handle the "status" property and are skipped if
disabled. Devices which are probed by the PCI enumeration don't check
that property. Fix it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Tested-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
pci: Only link pci_rom.o in some cases 2019-12-03T13:43:24+00:00 Tom Rini trini@konsulko.com 2019-11-27T01:40:59+00:00 923e211f8d92d67caa93125f1aff2ae123c6b9d5 The content of pci_rom.c is only used in a few cases. Only build and link in these cases to avoid a global variable as gcc doesn't always discard those when they are unused. Signed-off-by: Tom Rini <trini@konsulko.com> 
The content of pci_rom.c is only used in a few cases.  Only build and
link in these cases to avoid a global variable as gcc doesn't always
discard those when they are unused.

Signed-off-by: Tom Rini <trini@konsulko.com>
common: Move pci_init_board() out of common.h 2019-12-02T23:25:25+00:00 Simon Glass sjg@chromium.org 2019-11-14T19:57:47+00:00 2cf431c228776d9899dfb980086b86d4dd3b2473 This function can be dropped when all boards use driver model for PCI. For now, move it into init.h with a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> 
This function can be dropped when all boards use driver model for PCI. For
now, move it into init.h with a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq 2019-11-11T19:19:04+00:00 Tom Rini trini@konsulko.com 2019-11-11T19:19:04+00:00 0b73ef0c02313e651af4b0a8e206c7c4a198e7f8 - Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC. - Few bug fixes and updates related to SPI, hwconfig, ethernet, fsl-layerscape, pci, icid, PSCI 
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
  fsl-layerscape, pci, icid, PSCI
pci: layerscape: Only set EP CFG READY bit 2019-11-08T05:43:38+00:00 Pankaj Bansal pankaj.bansal@nxp.com 2019-10-14T11:43:19+00:00 05c81d98e4f3587180d26068b5925a08f3880dd2 In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit of pci controller is set, so that RC can read the config space of EP. While setting the config ready bit, LTSSM_EN bit in same register was also inadvertently getting cleared. This restarts the link training between RC and EP. Update code to just set the desired CFG_READY bit (bit 0), while leaving the other bits unchanged. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> 
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.

While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.

Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
arm: add initial support for the Phytium Durian Board 2019-11-07T23:01:13+00:00 liu hao steven_hao5189@outlook.com 2019-10-31T07:51:08+00:00 e3aafef4cf2d16e14e3bc02c3d8dbd434e305c19 This adds platform code and the device tree for the Phytium Durian Board. The initial support comprises the UART and the PCIE. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Steven Hao <liuhao@phytium.com.cn> 
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>

Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
pci: add DM based mpc85xx driver 2019-11-06T11:00:19+00:00 Heiko Schocher hs@denx.de 2019-10-14T09:29:39+00:00 b61cbbdcabbd56da83eed401b813766e2ef994dc add DM based PCI Configuration space access support for MPC85xx PCI Bridge. This driver is based on arch/powerpc/cpu/mpc85xx/pci.c In the old driver there is a fix for a hw issue on the TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I have no such hardware I did not port this part. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> 
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.c

In the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 2019-10-12T14:52:48+00:00 Tom Rini trini@konsulko.com 2019-10-12T14:52:48+00:00 9189d6f1e9c4ae40a14558636ed7b59b53c4c885 - Remember the device being emulated for Sandbox PCI - Update Kconfig options for FSP 1.0 - Drop RESET_BASE and RESET_SEG_SIZE that are no longer used 
- Remember the device being emulated for Sandbox PCI
- Update Kconfig options for FSP 1.0
- Drop RESET_BASE and RESET_SEG_SIZE that are no longer used
pci: mediatek: add PCIe controller support for MT7623 2019-10-11T14:09:58+00:00 Ryder Lee ryder.lee@mediatek.com 2019-08-22T10:26:49+00:00 42d37450e50b3a763d95fe1ff46499b9e564596e This adds PCIe controller support for MT7623. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> 
This adds PCIe controller support for MT7623.
This is adapted from the Linux version.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
sandbox: pci: Remember the device being emulated 2019-10-11T09:37:15+00:00 Simon Glass sjg@chromium.org 2019-09-21T20:32:41+00:00 6498fda140f526f82f87e057afb61ca23904770f Add a field to the PCI emulator per-device data which records which device is being emulated. This is useful when the emulator needs to check the device for something. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> 
Add a field to the PCI emulator per-device data which records which device
is being emulated. This is useful when the emulator needs to check the
device for something.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>