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<title>u-boot.git/drivers/pci, branch v2020.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2020.01-rc2</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2020.01-rc2'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2019-11-11T19:19:04Z</updated>
<entry>
<title>Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq</title>
<updated>2019-11-11T19:19:04Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-11-11T19:19:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0b73ef0c02313e651af4b0a8e206c7c4a198e7f8'/>
<id>urn:sha1:0b73ef0c02313e651af4b0a8e206c7c4a198e7f8</id>
<content type='text'>
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
  fsl-layerscape, pci, icid, PSCI
</content>
</entry>
<entry>
<title>pci: layerscape: Only set EP CFG READY bit</title>
<updated>2019-11-08T05:43:38Z</updated>
<author>
<name>Pankaj Bansal</name>
<email>pankaj.bansal@nxp.com</email>
</author>
<published>2019-10-14T11:43:19Z</published>
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<id>urn:sha1:05c81d98e4f3587180d26068b5925a08f3880dd2</id>
<content type='text'>
In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.

While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.

Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.

Signed-off-by: Pankaj Bansal &lt;pankaj.bansal@nxp.com&gt;
Reviewed-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>arm: add initial support for the Phytium Durian Board</title>
<updated>2019-11-07T23:01:13Z</updated>
<author>
<name>liu hao</name>
<email>steven_hao5189@outlook.com</email>
</author>
<published>2019-10-31T07:51:08Z</published>
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<id>urn:sha1:e3aafef4cf2d16e14e3bc02c3d8dbd434e305c19</id>
<content type='text'>
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Cc: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;

Signed-off-by: Steven Hao &lt;liuhao@phytium.com.cn&gt;
</content>
</entry>
<entry>
<title>pci: add DM based mpc85xx driver</title>
<updated>2019-11-06T11:00:19Z</updated>
<author>
<name>Heiko Schocher</name>
<email>hs@denx.de</email>
</author>
<published>2019-10-14T09:29:39Z</published>
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<id>urn:sha1:b61cbbdcabbd56da83eed401b813766e2ef994dc</id>
<content type='text'>
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.c

In the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.

Signed-off-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
</entry>
<entry>
<title>Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86</title>
<updated>2019-10-12T14:52:48Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-10-12T14:52:48Z</published>
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<id>urn:sha1:9189d6f1e9c4ae40a14558636ed7b59b53c4c885</id>
<content type='text'>
- Remember the device being emulated for Sandbox PCI
- Update Kconfig options for FSP 1.0
- Drop RESET_BASE and RESET_SEG_SIZE that are no longer used
</content>
</entry>
<entry>
<title>pci: mediatek: add PCIe controller support for MT7623</title>
<updated>2019-10-11T14:09:58Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2019-08-22T10:26:49Z</published>
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<id>urn:sha1:42d37450e50b3a763d95fe1ff46499b9e564596e</id>
<content type='text'>
This adds PCIe controller support for MT7623.
This is adapted from the Linux version.

Tested-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Signed-off-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
</content>
</entry>
<entry>
<title>sandbox: pci: Remember the device being emulated</title>
<updated>2019-10-11T09:37:15Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-21T20:32:41Z</published>
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<id>urn:sha1:6498fda140f526f82f87e057afb61ca23904770f</id>
<content type='text'>
Add a field to the PCI emulator per-device data which records which device
is being emulated. This is useful when the emulator needs to check the
device for something.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: rebase the patch against u-boot-x86/master to get it applied cleanly]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>sandbox: pci: Create a new sandbox_pci_read_bar() function</title>
<updated>2019-10-08T05:57:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:42Z</published>
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<id>urn:sha1:75d8f49481a5c260d0cf1024d41f0b29d57e0efe</id>
<content type='text'>
The code in swapcase can be used by other sandbox drivers. Move it into a
common place to allow this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: remove inclusion of &lt;asm/test.h&gt; in pci_sandbox.c]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: pci: Drop the first parameter in pci_x86_r/w_config()</title>
<updated>2019-10-08T05:57:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-01T03:23:18Z</published>
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<id>urn:sha1:a827ba910cdbcae6d0a1c2ce7b91b41d00218a4c</id>
<content type='text'>
This parameter is needed by the PCI driver-mode interface but is always
NULL on x86. There are a number of calls to this function so it makes
sense to minimise the parameters.

Adjust the x86 function to omit the first parameter, and introduce stub
functions to handle the conversion.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move acpi_s3.h to a common location</title>
<updated>2019-10-08T05:57:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:32Z</published>
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<id>urn:sha1:49a0f8cc964c612164ef101267f90266279409a7</id>
<content type='text'>
At present this hedaer is only available on x86. To allow sandbox to use
it for testing, move it to a common location.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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