u-boot.git/drivers/pci, branch v2021.01

Revert "arm64: a37xx: pci: Assert PERST# signal when unloading driver"

2020-12-28T08:42:06Z

This reverts commit 828d32621686aec593076d16445d39b9b8d49c05. This change revers code which asserting PERST# signal when unloading driver. Driver's remove callback is still there as it is used for other functionality. Asserting PERST# signal prior booting kernel is causing that A3720 boards (Turris MOX and Espressobin) with stable Linux kernel versions 4.14 and 4.19 are not able to detect some PCIe cards (e.g. Compex WLE200 and WLE900) and anymore. When PERST# signal is not asserted these cards are detected correctly. As this is regression for existing stable Linux kernel versions revert this problematic change in U-Boot. To make cards working with OpenWRT 4.14 kernel it is needed to disable link training prior booting kernel, which is already done in driver's remove callback. Described issue is in Linux kernel pci aardvark driver which is (hopefully) fixed in latest upstream versions. Latest upstream versions should be able to initialize PCIe bus and detects cards independently of the link training and PERST# signal state. So with this change, U-Boot on A3720 boards should be able to boot OpenWRT 4.14 kernel, stable 4.14 and 4.19 kernels and also latest mainline kernels. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese

pci: layerscape: fix a dead loop issue

2020-12-10T08:26:39Z

Fixes: commit 8ec619f8fd84 ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2") This added the PCIe EP nodes fixup of LX2160A, but it didn't update the condition value when there isn't a property 'apio-wins'. Signed-off-by: Hou Zhiqiang [Fixed checkpatch error] Signed-off-by: Priyanka Jain

armv8: lx2162a: Add Soc changes to support LX2162A

2020-12-10T08:26:39Z

LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal [Fixed whitespace errors] Signed-off-by: Priyanka Jain

pci: ls_pcie_g4: Add size check for config resource

2020-12-10T08:26:39Z

resource "config" is required to have minimum 4KB space to access all config space of PCI Express EP. Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain

pci: layerscape: Add size check for config resource

2020-12-10T08:26:39Z

resource "config" is required to have minimum 8KB space as per hardware documentation. Signed-off-by: Hou Zhiqiang Signed-off-by: Wasim Khan Reviewed-by: Priyanka Jain

pci: ls_pcie_g4: Print pcie controller number starting from 1

2020-12-10T08:26:38Z

Print pcie controller number starting from 1 Signed-off-by: Wasim Khan

pci: layerscape: Update print of pcie controller

2020-12-10T08:26:38Z

Print pcie controller number starting from 1 Signed-off-by: Wasim Khan [Trimmed subject] Signed-off-by: Priyanka Jain

dm: pci: fsl: Correct the workaround of erratum A-007815

2020-10-23T11:22:09Z

The register to enable/disable the write-permission of DBI RO registers should be accessed via the CFG_ADDR/CFG_DATA registers instead of accessing directly. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain

pci: layerscape: add a way of specifying additional iommu mappings

2020-10-23T11:22:09Z

In the current implementation, u-boot creates iommu mappings only for PCI devices enumarated at boot time thus does not take into account more dynamic scenarios such as SR-IOV or PCI hot-plug. Add an u-boot env var and a device tree property (to be used for example in more static scenarios such as hardwired PCI endpoints that get initialized later in the system setup) that would allow two things: - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number of VFs that will ever be created for it - for hot-plug case, specify the B.D.F with which the device will show up on the PCI bus More details can be found in the included documentation: arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra Signed-off-by: Laurentiu Tudor Reviewed-by: Priyanka Jain

pci: layerscape: move pci node search in a common function

2020-10-23T11:22:09Z

Fix duplication of this code by placing it in a common function. Furthermore, the resulting function will be re-used in upcoming patches. Signed-off-by: Laurentiu Tudor Reviewed-by: Priyanka Jain